Click here to Skip to main content
Click here to Skip to main content

Scalable Processor Arrays for Cybernetic Control

, 22 Dec 2012 GPL3
Architecture for scalable arrays of PIC processors; each processor is responsible for all aspects of control in a single dimension, using a PID algorithm.
We're sorry, but the article you are trying to view was deleted at 7 Jan 2013.

Please go to the Hardware & System Table of Contents to view the list of available articles in this section.
| Advertise | Privacy | Terms of Use | Mobile
Web01 | 2.8.1411023.1 | Last Updated 22 Dec 2012
Article Copyright 2011 by _beauw_
Everything else Copyright © CodeProject, 1999-2014
Layout: fixed | fluid