Click here to Skip to main content
       

C / C++ / MFC

 
QuestionRe: VC++6.0 menu limit? PinmemberChris Meech13-Dec-12 6:00 
AnswerRe: VC++6.0 menu limit? PinmemberMaximilien13-Dec-12 7:03 
GeneralRe: VC++6.0 menu limit? Pinmemberjschell12-Dec-12 8:55 
QuestionBit field ordering on Big-Endian (SPARC) processor PinmemberHolmes.Sherlock11-Dec-12 5:40 
Consider the code below:
 
#include <stdio.h>
#include <stdlib.h>

#define FORCE_CAST(var, type) *(type*)&var
 
struct processor_status_register
{
unsigned int cwp:5;
unsigned int et:1;
unsigned int ps:1;
unsigned int s:1;
unsigned int pil:4;
unsigned int ef:1;
unsigned int ec:1;
unsigned int reserved:6;
 
unsigned int c:1;
unsigned int v:1;
unsigned int z:1;
unsigned int n:1;
 
unsigned int ver:4;
unsigned int impl:4;
}__attribute__ ((__packed__));
 

 
struct registers
{
       unsigned long* registerSet;
       unsigned long* globalRegisters;
       unsigned long* cwptr;
       unsigned long wim, tbr, y, pc, npc;
       unsigned short registerWindows;
 
       /* Though Intel x86 architecture allows un-aligned memory
access, SPARC mandates memory accesses to be 8 byte aligned.
        Without __attribute__ ((aligned (8))) or a preceding dummy
byte e.g. unsigned short dummyByte, the code below crashes
        with a dreaded Bus error and Core dump. For more details,
follow the links below:
 
        http://blog.jgc.org/2007/04/debugging-solaris-bus-error-caused-by.html
        https://groups.google.com/forum/?fromgroups=#!topic/comp.unix.solaris/8SgFiMudGL4
*/
 
       struct processor_status_register __attribute__ ((aligned (8))) psr;
}__attribute__ ((__packed__));
 

int getBit(unsigned long bitStream, int position)
{
int bit;
bit = (bitStream & (1 << position)) >> position;
return bit;
}
 

char* showBits(unsigned long bitStream, int startPosition, int endPosition)
{
// Allocate one extra byte for NULL character
char* bits = (char*)malloc(endPosition - startPosition + 2);
int bitIndex;
for(bitIndex = 0; bitIndex <= endPosition; bitIndex++)
bits[bitIndex] = (getBit(bitStream, endPosition - bitIndex)) ? '1' : '0';
bits[bitIndex] = '\0';
return bits;
}
 

int main()
{
struct registers sparcRegisters; short isLittleEndian;
 
// Check for Endianness
        unsigned long checkEndian = 0x00000001;
        if(*((char*)(&checkEndian)))
            {printf("Little Endian\n"); isLittleEndian = 1;} // Little
Endian architecture detected
        else
            {printf("Big Endian\n"); isLittleEndian = 0;} // Big
Endian architecture detected
 
unsigned long registerValue = 0xF30010A7;
unsigned long swappedRegisterValue = isLittleEndian ? registerValue :
__builtin_bswap32(registerValue);
        sparcRegisters.psr = FORCE_CAST(swappedRegisterValue, struct
processor_status_register);
registerValue = isLittleEndian ? FORCE_CAST (sparcRegisters.psr,
unsigned long) : __builtin_bswap32(FORCE_CAST (sparcRegisters.psr,
unsigned long));
printf("\nPSR=0x%0X, IMPL=%u, VER=%u, CWP=%u\n", registerValue,
sparcRegisters.psr.impl, sparcRegisters.psr.ver,
sparcRegisters.psr.cwp);
printf("PSR=%s\n",showBits(registerValue, 0, 31));
 
sparcRegisters.psr.cwp = 7;
sparcRegisters.psr.et = 1;
sparcRegisters.psr.ps = 0;
sparcRegisters.psr.s = 1;
sparcRegisters.psr.pil = 0;
sparcRegisters.psr.ef = 0;
sparcRegisters.psr.ec = 0;
sparcRegisters.psr.reserved = 0;
sparcRegisters.psr.c = 0;
sparcRegisters.psr.v = 0;
sparcRegisters.psr.z = 0;
sparcRegisters.psr.n = 0;
sparcRegisters.psr.ver = 3;
sparcRegisters.psr.impl = 0xF;
registerValue = isLittleEndian ? FORCE_CAST (sparcRegisters.psr,
unsigned long) : __builtin_bswap32(FORCE_CAST (sparcRegisters.psr,
unsigned long));
printf("\nPSR=0x%0X, IMPL=%u, VER=%u, CWP=%u\n", registerValue,
sparcRegisters.psr.impl, sparcRegisters.psr.ver,
sparcRegisters.psr.cwp);
printf("PSR=%s\n\n",showBits(registerValue, 0, 31));
 
return 0;
}
 

//////////////////////////////////////////////////////////////////////////////
 

I have used gcc-4.7.2 on Solaris 10 on SPARC to compile the following
code to produce the Big-Endian output:
 
Big Endian
 
PSR=0xF30010A7, IMPL=3, VER=15, CWP=20
PSR=11110011000000000001000010100111
 
PSR=0x3F00003D, IMPL=15, VER=3, CWP=7
PSR=00111111000000000000000000111101
 

//////////////////////////////////////////////////////////////////////////////
 

I have used gcc-4.4 on Ubuntu-10.04 on Intel-x86 to compile the
following code to produce the Little-Endian output:
 
Little Endian
 
PSR=0xF30010A7, IMPL=15, VER=3, CWP=7
PSR=11110011000000000001000010100111
 
PSR=0xF30000A7, IMPL=15, VER=3, CWP=7
PSR=11110011000000000000000010100111
 

//////////////////////////////////////////////////////////////////////////////
 

While the later one is as expected, can anyone please explain the
Big-Endian counterpart? Considering the showBits() method to be
correct, how can PSR=0x3F00003D give rise to IMPL=15, VER=3, CWP=7
values? How is the bit-field is being arranged and interpreted in
memory on a Big-Endian system?
AnswerRe: Bit field ordering on Big-Endian (SPARC) processor PinmvpRichard MacCutchan11-Dec-12 9:45 
AnswerRe: Bit field ordering on Big-Endian (SPARC) processor PinmemberPeter_in_278011-Dec-12 10:50 
GeneralRe: Bit field ordering on Big-Endian (SPARC) processor PinmemberHolmes.Sherlock11-Dec-12 12:27 
GeneralRe: Bit field ordering on Big-Endian (SPARC) processor PinmemberPeter_in_278011-Dec-12 12:46 
GeneralRe: Bit field ordering on Big-Endian (SPARC) processor PinmemberHolmes.Sherlock11-Dec-12 12:48 
QuestionThread Pinmembermessages11-Dec-12 1:25 

General General    News News    Suggestion Suggestion    Question Question    Bug Bug    Answer Answer    Joke Joke    Rant Rant    Admin Admin   

Use Ctrl+Left/Right to switch messages, Ctrl+Up/Down to switch threads, Ctrl+Shift+Left/Right to switch pages.


Advertise | Privacy | Mobile
Web03 | 2.8.141022.2 | Last Updated 25 Oct 2014
Copyright © CodeProject, 1999-2014
All Rights Reserved. Terms of Service
Layout: fixed | fluid