The product of this project will give a tool in terms of software, capable of extracting a vigorous testing for a given digital module (which is a logical unit) under a mass production.
Today, we have lots of testing algorithms with us, efficient enough to give a reliable result with some bearable errors. But when we cannot afford even a single error in our product, we choose to perform a vigorous-testing on this product where all the possible input-output conditions are tested as per the specifications. In the scope of its software requirement specifications (SRS) document, we name the product as "logic circuit testing tool". This SRS explains the requirement and expectations of the system to be developed and its probable users.
Scope of the project
The logic circuit testing tool (LCTT), as developed, will derive a vigorous testing of a given circuit for a given input signal set (0 or 1) on its input pins. The system will create input patterns to be fed into the input lines of the circuit under test and captures the output from its output lines to create a truth table for the circuit. This communication between 'LCTT' software and the given circuit occurs through the 'LPT' port of the computer (D-25 printer port/Parallel Port).
- Although the software will not be highly dependent on any type of computer-hardware. It will be capable to work on any PC-configuration higher than "386-intel", but the performance will be much faster on 'Pentium' configurations.
- The software will first develop a database with a masterpiece that has already been assured to be a perfect one by manual testing. After that, the software compares the truth table for other pieces under test with the database. For any mismatch, the system reports for the faulty circuit.
- The system will work only for the passive logic circuits, without any oscillators or power sources in them. The use of vibrators is also not involved.
- The system treats the unit-under-test just as a black box and does not do anything inside it. It is concerned to the input and corresponding output relations only. Hence the two different circuits equivalent to each other in their I/O results will be treated equally. For example, if unit under test is working like an XOR gate, the system will not detect if it is a direct XOR-gate I.C. or is composed of NAND or NOR gates. The result will be based on end point truth tables only.
The product LCTT In brief
- The product software interfaces with a masterpiece circuit (whose identical units are to be produced and tested), through the parallel port of computer to create a database truth table.
- Then the other identical units are attached to the computer in prescribed manner on the parallel port and a new truth table is created for comparison with the database truth table.
- For any mismatch, the unit is reported to be faulty.
- The system software needs not to tell the cause or spot of the fault.
- Separate modules for sequential and the non-sequential logic circuits.
- The user of the system is expected to be trained to make proper connections as expected between the unit under test and the parallel port of the computer.
- Any error in connection may lead to the failure of the system or faulty-results or even damage to the computer
- A brief knowledge of parallel port of computer is desirable.
- After making proper connections, the user is required to follow the instructions provided by the system itself.
- The input lines of the circuit under test are required to be connected to the output lines of the 'LPT' port of the computer (Pin numbers).
- The output lines of the circuit under test are to be connected to the input lines of the parallel port of the system (Pin Numbers).
Logic Circuit Testing tool ( Program in C )
The author has taken his best efforts in preparing this document. The author makes no representation or warranties with respect to the accuracy or completeness of this document & specifically disclaims any implied warranties of fitness of the content for any specific purpose. The author takes no responsibilities for the success of work or expected outcome with the rules stated herein. The author will not be responsible and liable for any (financial or any other) gain or loss or any commercial damages.