Xilinx FPGA with AVRILOS

/***************************************************************************
 Project:		AVRILOS
 Title:         FPGA SSI Communication module
 Author:		Ilias Alexopoulos
 Version:		2.00
 Last updated:	05-Feb-2011
 Target:		AT90S8535/ATMEGA163
 File:			fpgassi.c

* Support E-mail:
* avrilos@ilialex.gr
* 
* license: See license.txt on root directory (CDDL)
*

* DESCRIPTION
* Communicate with FPGA Synchronous Serial Interface
* Code adopted from AVR assembly version back on 2002.
*
***************************************************************************/
#include <avr/io.h>

#include "../includes/types.h"
#include "../includes/settings.h"
#include "../Utils/delay.h"
#include "fpgassi.h"
//#include "../../Uart/Uart.h"

#define	MCUDataInput do{ cbi(c_IFCDDR, b_MCUData); }while(0)
#define	MCUDataOutput do{ sbi(c_IFCDDR, b_MCUData); }while(0)
#define	MCUClkOutput do{ sbi(c_IFCDDR, b_MCUClk); }while(0)
#define	MCUFrameOutput do{ sbi(c_IFCDDR, b_MCUFrame); }while(0)
#define	SetMCUData do{ sbi(c_IFCPORT, b_MCUData); }while(0)
#define	ClrMCUData do{ cbi(c_IFCPORT, b_MCUData); }while(0)
#define	MCUClk	do{ sbi(c_IFCPORT, b_MCUClk); \
					cbi(c_IFCPORT, b_MCUClk); \
					}while(0)
#define	MCUClkHi	do{ sbi(c_IFCPORT, b_MCUClk); \
					}while(0)
#define	MCUClkLo	do{ cbi(c_IFCPORT, b_MCUClk); \
					}while(0)

#define	SetMCUFrame do{	sbi(c_IFCPORT, b_MCUFrame); }while(0)
#define	ClrMCUFrame do{	cbi(c_IFCPORT, b_MCUFrame); }while(0)


#ifndef MOD_FPGAXCS_SSI
_INLINE_ void f_InitSSI(void) {}
_INLINE_ void f_FPGAWr(INT8U addr, INT8U data) {}
_INLINE_ INT8U f_FPGARd(INT8U addr) { return 0; }
_INLINE_ void f_MCUClk(void) {}
_INLINE_ void f_FPGA_BitTx(INT8U data, INT8U shcnt) {}
_INLINE_ INT8U f_FPGA_BitRx(INT8U shcnt) { return 0; }

#else


void f_InitSSI(void)
{
	MCUFrameOutput;
	MCUClkOutput;
	MCUDataInput;

	cbi(c_IFCPORT, b_MCUClk);
	ClrMCUFrame;
	
/****************************************
	; check for Done
	; if OK then Configuration Complete!
	; Else Fail...
****************************************/
	//while(!(inp(c_CFGPIN) & (1<<b_Done) ));
}

void f_FPGAWr(INT8U addr, INT8U data)
{

	MCUDataOutput;
	SetMCUFrame;
	
	/* bit 7 -> 0 */
	addr &= (~ FPGARD);
	// f_Uart_PutChar(addr);
	f_FPGA_BitTx(addr, 8);
	/*  data length = 8 */
	f_FPGA_BitTx(data, 8);

	ClrMCUFrame;
	MCUDataInput;
}

void f_MCUClk(void)
{
	MCUClk;
}

INT8U f_FPGARd(INT8U addr)
{
	INT8U v_data;

	MCUDataOutput;
	SetMCUFrame;
	
	/* bit 7 -> 1 */
	addr |= FPGARD;
	/*  regaddr length = 5 */
	f_FPGA_BitTx(addr, 8);

	MCUDataInput;

	/*  data length = 8 */
	v_data = f_FPGA_BitRx(8);

	ClrMCUFrame;
	return v_data;
}

void f_FPGA_BitTx(INT8U data, INT8U shcnt)
{
	INT8U i;

	for(i=0; i<shcnt; i++)
	{
		/* according to bit 7 (MSB first) */
		if(data & 0x80)
		{
			SetMCUData;
			// f_Uart_PutChar('1');
		}
		else
		{
			ClrMCUData;
			// f_Uart_PutChar('0');
		}
		MCUClk;				/* clock data in FPGA */
		data = data << 1;
	}
}


INT8U f_FPGA_BitRx(INT8U shcnt)
{

	INT8U i;
	INT8U v_data = 0;

	for(i=0; i<shcnt; i++)
	{
		//MCUClk;				/* clock data out of FPGA */
		MCUClkHi;
		/* according to bit 7 (MSB first) */
		if ( inp(c_IFCPIN) & (1 << b_MCUData) ) v_data = (v_data << 1) | 1;
		else v_data = (v_data << 1);
		MCUClkLo;
	}

	return v_data;
}


#endif