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Circuit Engine

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18 Oct 2018GPL355 min read 248.1K   8.6K   212  
A System for Simulation and Analysis of Logic Circuits
 
(i)(CEngine): Creating source level (V&G)....
(i)(CircuitElement CE_NONAME.0): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.0): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Renaming...
(i)(CircuitElement Source(V&G).0): New name is OK.
(i)(Gate):(Type[Voltage],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[Ground],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(c)(CEngine): CE Empty:Source(V&G) is added into circuit.
(c)(CEngine): compilation started (D:\_Courses\_PASTU~1\DO6114~1\CMPE40~1\CEngine.net\Release\4BITAD~1\4BITAD~1.CES)....
Initializing BreadBoard Node Table(r30,c4)...
BreadBoard Node Table is ready.
Initializing BreadBoard Node Map Table(h6)...
BreadBoard Node Map Table is ready.
(i)(CircuitElement CE_NONAME.1): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.1): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Renaming...
(i)(CircuitElement FullAdder.1): New name is OK.
(c)(CEngine): CE CHIP:FullAdder is now setting up by in-script information ....
(i)(CircuitElement FullAdder.1): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[5])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[7])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[2],OutAsLeg[6])::SetProps.() : properties OK.
(i)(CircuitElement FullAdder.1): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(c)(CEngine): Gate List is OK for FullAdder.1..
(c)(CEngine): Gate connection process is starting for FullAdder.1....
(c)(CEngine): Gate connection process is completed..
(c)(CEngine): CE CHIP:FullAdder is added into circuit.
(i)(CircuitElement CE_NONAME.2): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.2): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Renaming...
(i)(CircuitElement FullAdder.2): New name is OK.
(c)(CEngine): CE CHIP:FullAdder is now setting up by in-script information ....
(i)(CircuitElement FullAdder.2): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[5])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[7])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[2],OutAsLeg[6])::SetProps.() : properties OK.
(i)(CircuitElement FullAdder.2): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(c)(CEngine): Gate List is OK for FullAdder.2..
(c)(CEngine): Gate connection process is starting for FullAdder.2....
(c)(CEngine): Gate connection process is completed..
(c)(CEngine): CE CHIP:FullAdder is added into circuit.
(i)(CircuitElement CE_NONAME.3): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.3): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.3): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.3): Renaming...
(i)(CircuitElement FullAdder.3): New name is OK.
(c)(CEngine): CE CHIP:FullAdder is now setting up by in-script information ....
(i)(CircuitElement FullAdder.3): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[5])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[7])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[2],OutAsLeg[6])::SetProps.() : properties OK.
(i)(CircuitElement FullAdder.3): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(c)(CEngine): Gate List is OK for FullAdder.3..
(c)(CEngine): Gate connection process is starting for FullAdder.3....
(c)(CEngine): Gate connection process is completed..
(c)(CEngine): CE CHIP:FullAdder is added into circuit.
(i)(CircuitElement CE_NONAME.4): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.4): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.4): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.4): Renaming...
(i)(CircuitElement FullAdder.4): New name is OK.
(c)(CEngine): CE CHIP:FullAdder is now setting up by in-script information ....
(i)(CircuitElement FullAdder.4): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[5])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[7])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[2],OutAsLeg[6])::SetProps.() : properties OK.
(i)(CircuitElement FullAdder.4): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(c)(CEngine): Gate List is OK for FullAdder.4..
(c)(CEngine): Gate connection process is starting for FullAdder.4....
(c)(CEngine): Gate connection process is completed..
(c)(CEngine): CE CHIP:FullAdder is added into circuit.
(i)(CEngine): compilation completed....

LISTING CURRENT CIRCUIT ELEMENTS:

BREADBOARD : 30 rows, 4 cols and 6 holes in a node.

Gate List CE Source(V&G).id_0 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_0 (00000000), G = leg_0 (00000000)
Voltage(003C2580)(leg_0).1 >> 0 ()
Ground(003C25B8)(leg_0).2 >> 0 ()

Gate List CE FullAdder.id_1 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_1 (00000000), G = leg_5 (00000000)
Input(003C81A8)(leg_2).1 >> 1 ( 00000000 )
Input(003C81E0)(leg_3).2 >> 1 ( 00000000 )
Input(003C8218)(leg_4).3 >> 1 ( 00000000 )
XOR(003C8250)(leg_0).4 >> 2 ( 003C81A8  003C81E0 )
AND(003C8288)(leg_0).5 >> 2 ( 003C81A8  003C81E0 )
XOR(003C82C0)(leg_7).6 >> 2 ( 003C8250  003C8218 )
AND(003C82F8)(leg_0).7 >> 2 ( 003C8250  003C8218 )
OR(003C8330)(leg_6).8 >> 2 ( 003C8288  003C82F8 )

Gate List CE FullAdder.id_2 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_1 (00000000), G = leg_5 (00000000)
Input(003C8450)(leg_2).1 >> 1 ( 00000000 )
Input(003C8488)(leg_3).2 >> 1 ( 00000000 )
Input(003C84C0)(leg_4).3 >> 1 ( 00000000 )
XOR(003C84F8)(leg_0).4 >> 2 ( 003C8450  003C8488 )
AND(003C8530)(leg_0).5 >> 2 ( 003C8450  003C8488 )
XOR(003C8568)(leg_7).6 >> 2 ( 003C84F8  003C84C0 )
AND(003C85A0)(leg_0).7 >> 2 ( 003C84F8  003C84C0 )
OR(003C85D8)(leg_6).8 >> 2 ( 003C8530  003C85A0 )

Gate List CE FullAdder.id_3 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_1 (00000000), G = leg_5 (00000000)
Input(003C86F8)(leg_2).1 >> 1 ( 00000000 )
Input(003C8730)(leg_3).2 >> 1 ( 00000000 )
Input(003C8768)(leg_4).3 >> 1 ( 00000000 )
XOR(003C87A0)(leg_0).4 >> 2 ( 003C86F8  003C8730 )
AND(003C87D8)(leg_0).5 >> 2 ( 003C86F8  003C8730 )
XOR(003C8810)(leg_7).6 >> 2 ( 003C87A0  003C8768 )
AND(003C8848)(leg_0).7 >> 2 ( 003C87A0  003C8768 )
OR(003C8880)(leg_6).8 >> 2 ( 003C87D8  003C8848 )

Gate List CE FullAdder.id_4 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_1 (00000000), G = leg_5 (00000000)
Input(003C89A0)(leg_2).1 >> 1 ( 00000000 )
Input(003C89D8)(leg_3).2 >> 1 ( 00000000 )
Input(003C8A10)(leg_4).3 >> 1 ( 00000000 )
XOR(003C8A48)(leg_0).4 >> 2 ( 003C89A0  003C89D8 )
AND(003C8A80)(leg_0).5 >> 2 ( 003C89A0  003C89D8 )
XOR(003C8AB8)(leg_7).6 >> 2 ( 003C8A48  003C8A10 )
AND(003C8AF0)(leg_0).7 >> 2 ( 003C8A48  003C8A10 )
OR(003C8B28)(leg_6).8 >> 2 ( 003C8A80  003C8AF0 )

END OF CIRCUIT LIST


Deallocating BreadBoard Node Table...
Deallocating BreadBoard Node Map Table...
Deallocation of BreadBoard is completed.

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License

This article, along with any associated source code and files, is licensed under The GNU General Public License (GPLv3)


Written By
Emre Guldogan
Engineer Siemens
Turkey Turkey
I've graduated from computer engineering department in 2004 July, and developed the Circuit Engine as my graduation project at Eastern Mediterranean University (EMU). I've also graduated from MBA, Istanbul University in 2008 February. From 2004 until now, I've developed many web sites (B2B, B2C). Currently work for Siemens AG (http://siemens.com/ingenuityforlife) as a R&D Engineer (IoT) and I still continue to develop my personal projects about encryption algorithms, maths, OpenGL, Stock Exchange Market Analyses and Real-time Systems, MultiThreaded Applications and Web Solutions (mostly ASP.NET C#, JQuery/JS, MVC, WinForms, Win/Web Services, T-SQL and less PHP, ASP, MySQL and some possible other methods about problem solving if necessary). Also personal profession of photography : https://www.instagram.com/egldgn/


Circuit Engine base URL : https://sites.google.com/view/circuitengine


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Posted 23 Mar 2008

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