CEngineLog_06.07.04_13.12.40.txt
(i)(CEngine): Creating source level (V&G)....
(i)(CircuitElement CE_NONAME.0): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.0): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Renaming...
(i)(CircuitElement Source(V&G).0): New name is OK.
(i)(Gate):(Type[Voltage],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[Ground],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(c)(CEngine): CE Empty:Source(V&G) is added into circuit.
(c)(CEngine): compilation started (Copyoftry.cesl)....
Initializing BreadBoard Node Table(r50,c6)...
BreadBoard Node Table is ready.
Initializing BreadBoard Node Map Table(h5)...
BreadBoard Node Map Table is ready.
(i)(CircuitElement CE_NONAME.1): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.1): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Renaming...
(i)(CircuitElement FullAdder.1): New name is OK.
(c)(CEngine): CE CHIP:FullAdder is now setting up by in-script information ....
(i)(CircuitElement FullAdder.1): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(CircuitElement FullAdder.1): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[5])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[6])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[2],OutAsLeg[7])::SetProps.() : properties OK.
(c)(CEngine): Gate List is OK for FullAdder.1..
(c)(CEngine): Gate connection process is starting for FullAdder.1....
(c)(CEngine): Gate connection process is completed..
(c)(CEngine): CE CHIP:FullAdder is added into circuit.
(i)(CEngine): compilation completed....
LISTING COMPILED CIRCUIT:
Gate List CE Source(V&G).id_0 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_0 (00000000), G = leg_0 (00000000)
Voltage(003C08E8)(leg_0).1 >> 0 ()
Ground(003C0920)(leg_0).2 >> 0 ()
Gate List CE FullAdder.id_1 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_1 (00000000), G = leg_5 (00000000)
Input(003C7608)(leg_2).1 >> 1 ( 00000000 )
Input(003C7640)(leg_3).2 >> 1 ( 00000000 )
Input(003C7678)(leg_4).3 >> 1 ( 00000000 )
XOR(003C76B0)(leg_0).4 >> 2 ( 003C7608 003C7640 )
AND(003C76E8)(leg_0).5 >> 2 ( 003C7608 003C7640 )
XOR(003C7720)(leg_6).6 >> 2 ( 003C7608 003C7678 )
AND(003C7758)(leg_0).7 >> 2 ( 003C7608 003C7678 )
OR(003C7790)(leg_7).8 >> 2 ( 003C7608 003C7640 )
END OF CIRCUIT LIST
(i)(CircuitElement CE_NONAME.2): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.2): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Renaming...
(i)(CircuitElement LED.2): New name is OK.
(i)(CircuitElement LED.2): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(CircuitElement LED.2): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(c)(CEngine): CE LED:LED is added into circuit.
Deallocating BreadBoard Node Table...
Deallocating BreadBoard Node Map Table...
Deallocation of BreadBoard is completed.