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Circuit Engine

, 20 Dec 2010
A System for Simulation and Analysis of Logic Circuits
cesl_cec_examples.zip
Examples
4BitAdder
4bitAdder.cesl
74LS08
74LS08.CESL
Async1
Async1.cesl
ASYNC1~1.cec
Dual4InputMux
74153.pdf
DUAL4I~1.cec
DUAL4INPUTMUX.CESL
ExPage58
Page58.cesl
FullAdder
FULLAD~1.cec
fULLaDDER.CESL
FunctionF
FunctionF.cesl
CircuitEngine_-_Executable.zip
4bitAdder.cesl
74LS08.cec
74LS08.CESL
Asynchronous
Asynchronous.cec
Asynchronous.cesl
74153.pdf
DUAL4INPUTMUX.cec
DUAL4INPUTMUX.CESL
Page58.cesl
FullAdder.cec
FullAdder.CESL
FunctionF.cesl
circuitengine_code_files.zip
Debug
C.pch
CEngine.exe
CEngine.ilk
CEngine.obj
CEngine.pdb
CEngine.sbr
try.cesl
vc70.idb
vc70.pdb
Release
4BitAdder
4bitAdder.cesl
74LS08
74LS08.CESL
Async1
Async1.cesl
ASYNC1~1.cec
C.pch
C.pdb
CEngine.exe
CEngine.obj
DENEME.CESL
Dual4InputMux
74153.pdf
DUAL4I~1.cec
DUAL4INPUTMUX.CESL
empty.cesl
ExPage58
Page58.cesl
FF.cesl
FullAdder
FULLAD~1.cec
fULLaDDER.CESL
FunctionF
FunctionF.cesl
InitialScreen.bmp
Thumbs.db
Many.CESL
Page58.cesl
SavedLogs
try.cesl
vc70.idb
circuitengine_code_files_vs6.0.zip
C.pch
CEngine.exe
CEngine.ilk
CEngine.obj
CEngine.pdb
CEngine.sbr
try.cesl
vc70.idb
vc70.pdb
4bitAdder.cesl
74LS08.CESL
Async1.cesl
ASYNC1~1.cec
C.pch
C.pdb
CEngine.exe
CEngine.obj
DENEME.CESL
74153.pdf
DUAL4I~1.cec
DUAL4INPUTMUX.CESL
empty.cesl
Page58.cesl
FF.cesl
FULLAD~1.cec
fULLaDDER.CESL
FunctionF.cesl
InitialScreen.bmp
Thumbs.db
Many.CESL
Page58.cesl
try.cesl
vc70.idb
circuitengine_code_files_vs6.0_vs8.0.zip
4bitAdder.cesl
74LS08.CESL
Async1.cesl
ASYNC1~1.cec
Counter.cec
Counter.cesl
DUAL4I~1.cec
DUAL4INPUTMUX.CESL
FULLAD~1.cec
fULLaDDER.CESL
FunctionF.cesl
Page58.cesl
try.cesl
glut-3.7.6-bin.zip
glut-3.7.6-bin
glut.def
glut32.dll
glut32.lib
glut-3.spec.zip
(i)(CEngine): Creating source level (V&G)....
(i)(CircuitElement CE_NONAME.0): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.0): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Renaming...
(i)(CircuitElement Source(V&G).0): New name is OK.
(i)(Gate):(Type[Voltage],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[Ground],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(c)(CEngine): CE Empty:Source(V&G) is added into circuit.
(c)(CEngine): File is reading now (D:\_Courses\CMPE40~1\CEngine.net\Release\FULLAD~1\FULLAD~1.cec)....
(c)(CEngine): File ID is OK, the Circuit is Loading....
(c)(CEngine): Setting up the BreadBoard information....
Initializing BreadBoard Node Table(r20,c5)...
BreadBoard Node Table is ready.
Initializing BreadBoard Node Map Table(h5)...
BreadBoard Node Map Table is ready.
(c)(CEngine): BreadBoard is ready..
(i)(CircuitElement CE_NONAME.1): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.1): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Renaming...
(i)(CircuitElement FullAdder.1): New name is OK.
(i)(CircuitElement FullAdder.1): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[8])::SetProps.() : properties OK.
(i)(CircuitElement FullAdder.1): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[5])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[2],OutAsLeg[6])::SetProps.() : properties OK.
(c)(CEngine): CE CHIP:FullAdder is added into circuit.
(i)(CircuitElement CE_NONAME.2): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.2): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Renaming...
(i)(CircuitElement LED.2): New name is OK.
(i)(CircuitElement LED.2): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(CircuitElement LED.2): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(c)(CEngine): CE LED:LED is added into circuit.
(i)(CircuitElement CE_NONAME.3): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.3): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.3): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.3): Renaming...
(i)(CircuitElement LED.3): New name is OK.
(i)(CircuitElement LED.3): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(CircuitElement LED.3): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(c)(CEngine): CE LED:LED is added into circuit.
(i)(CircuitElement CE_NONAME.4): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.4): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.4): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.4): Renaming...
(i)(CircuitElement .4): New name is OK.
(i)(CircuitElement .4): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[4])::SetProps.() : properties OK.
(i)(CircuitElement .4): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .4): Renaming...
(i)(CircuitElement CABLE.4): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.5): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.5): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.5): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.5): Renaming...
(i)(CircuitElement .5): New name is OK.
(i)(CircuitElement .5): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[5])::SetProps.() : properties OK.
(i)(CircuitElement .5): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .5): Renaming...
(i)(CircuitElement CABLE.5): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.6): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.6): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.6): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.6): Renaming...
(i)(CircuitElement .6): New name is OK.
(i)(CircuitElement .6): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(CircuitElement .6): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .6): Renaming...
(i)(CircuitElement CABLE.6): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.7): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.7): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.7): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.7): Renaming...
(i)(CircuitElement .7): New name is OK.
(i)(CircuitElement .7): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(CircuitElement .7): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .7): Renaming...
(i)(CircuitElement CABLE.7): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.8): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.8): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.8): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.8): Renaming...
(i)(CircuitElement .8): New name is OK.
(i)(CircuitElement .8): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(CircuitElement .8): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .8): Renaming...
(i)(CircuitElement CABLE.8): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.9): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.9): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.9): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.9): Renaming...
(i)(CircuitElement .9): New name is OK.
(i)(CircuitElement .9): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(CircuitElement .9): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .9): Renaming...
(i)(CircuitElement CABLE.9): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.10): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.10): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.10): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.10): Renaming...
(i)(CircuitElement .10): New name is OK.
(i)(CircuitElement .10): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[17])::SetProps.() : properties OK.
(i)(CircuitElement .10): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .10): Renaming...
(i)(CircuitElement CABLE.10): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.11): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.11): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.11): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.11): Renaming...
(i)(CircuitElement .11): New name is OK.
(i)(CircuitElement .11): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(CircuitElement .11): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .11): Renaming...
(i)(CircuitElement CABLE.11): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.12): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.12): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.12): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.12): Renaming...
(i)(CircuitElement .12): New name is OK.
(i)(CircuitElement .12): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[17])::SetProps.() : properties OK.
(i)(CircuitElement .12): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .12): Renaming...
(i)(CircuitElement CABLE.12): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.13): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.13): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.13): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.13): Renaming...
(i)(CircuitElement .13): New name is OK.
(i)(CircuitElement .13): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[17])::SetProps.() : properties OK.
(i)(CircuitElement .13): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .13): Renaming...
(i)(CircuitElement CABLE.13): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.14): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.14): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.14): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.14): Renaming...
(i)(CircuitElement .14): New name is OK.
(i)(CircuitElement .14): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[17])::SetProps.() : properties OK.
(i)(CircuitElement .14): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .14): Renaming...
(i)(CircuitElement CABLE.14): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.15): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.15): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.15): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.15): Renaming...
(i)(CircuitElement .15): New name is OK.
(i)(CircuitElement .15): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[17])::SetProps.() : properties OK.
(i)(CircuitElement .15): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .15): Renaming...
(i)(CircuitElement CABLE.15): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.16): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.16): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.16): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.16): Renaming...
(i)(CircuitElement .16): New name is OK.
(i)(CircuitElement .16): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[17])::SetProps.() : properties OK.
(i)(CircuitElement .16): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .16): Renaming...
(i)(CircuitElement CABLE.16): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(c)(CEngine): In-CircuitElement connections completed, printing retrieved circuit (D:\_Courses\CMPE40~1\CEngine.net\Release\FULLAD~1\FULLAD~1.cec).

LISTING CURRENT CIRCUIT ELEMENTS:

BREADBOARD : 20 rows, 5 cols and 5 holes in a node.

Gate List CE Source(V&G).id_0 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_0 (00000000), G = leg_0 (00000000)
Voltage(003C2580)(leg_0).1 >> 0 ()
Ground(003C25B8)(leg_0).2 >> 0 ()

Gate List CE FullAdder.id_1 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_8 (00000000), G = leg_4 (00000000)
Input(003C6D30)(leg_1).1 >> 1 ( 00000000 )
Input(003C6D68)(leg_2).2 >> 1 ( 00000000 )
Input(003C6DA0)(leg_3).3 >> 1 ( 00000000 )
XOR(003C6DD8)(leg_0).4 >> 2 ( 003C6D30  003C6D68 )
AND(003C6E10)(leg_0).5 >> 2 ( 003C6D30  003C6D68 )
XOR(003C6E48)(leg_5).6 >> 2 ( 003C6DD8  003C6DA0 )
AND(003C6E80)(leg_0).7 >> 2 ( 003C6DD8  003C6DA0 )
OR(003C6EB8)(leg_6).8 >> 2 ( 003C6E10  003C6E80 )

Empty CE : LED

Empty CE : LED

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

END OF CIRCUIT LIST


(c)(CEngine): (Re)plugging process is initiated (D:\_Courses\CMPE40~1\CEngine.net\Release\FULLAD~1\FULLAD~1.cec).
(c)(CEngine): Plugging FullAdder.
(c)(CEngine): Plugging LED.
(c)(CEngine): Plugging LED.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): (Re)plugging process is completed.
(c)(CEngine): Circuit is printing after (replugging process).

LISTING CURRENT CIRCUIT ELEMENTS:

BREADBOARD : 20 rows, 5 cols and 5 holes in a node.

Gate List CE Source(V&G).id_0 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_0 (00000000), G = leg_0 (00000000)
Voltage(003C2580)(leg_0).1 >> 0 ()
Ground(003C25B8)(leg_0).2 >> 0 ()

Gate List CE FullAdder.id_1 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_8 (003C2580), G = leg_4 (003C25B8)
Input(003C6D30)(leg_1).1 >> 1 ( 003C2580 )
Input(003C6D68)(leg_2).2 >> 1 ( 003C2580 )
Input(003C6DA0)(leg_3).3 >> 1 ( 003C2580 )
XOR(003C6DD8)(leg_0).4 >> 2 ( 003C6D30  003C6D68 )
AND(003C6E10)(leg_0).5 >> 2 ( 003C6D30  003C6D68 )
XOR(003C6E48)(leg_5).6 >> 2 ( 003C6DD8  003C6DA0 )
AND(003C6E80)(leg_0).7 >> 2 ( 003C6DD8  003C6DA0 )
OR(003C6EB8)(leg_6).8 >> 2 ( 003C6E10  003C6E80 )

Empty CE : LED

Empty CE : LED

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

Empty CE : CABLE

END OF CIRCUIT LIST


(i)(CircuitElement CE_NONAME.17): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.17): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.17): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.17): Renaming...
(i)(CircuitElement CABLE.17): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
Deallocating BreadBoard Node Table...
Deallocating BreadBoard Node Map Table...
Deallocation of BreadBoard is completed.

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License

This article, along with any associated source code and files, is licensed under The GNU General Public License (GPLv3)

About the Author

Emre Guldogan
Team Leader
Turkey Turkey
I've graduated from computer engineering department in 2004 July, and developed the Circuit Engine as my graduation project at Eastern Mediterranean University (EMU). I've also graduated from MBA, Istanbul University in 2008 February. From 2004 until now, I've developed many web sites (B2B, B2C). Currently work for Dogan Online/ekolay.net as a software engineer and team leader. I still continue to develop my personal projects about encryption algorithms, maths, OpenGL and Real-time Systems and Web Solutions (mostly ASP.NET C#, JQuery/JS, MVC, WinForms, Win/Web Services, T-SQL and less PHP, ASP, MySQL and some possible other methods about problem solving if necessary).
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