AVRILOS SysTick Timer enhancements

grilialex

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8 Nov 2011CDDL9 min read

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Bug fixes and enhancements on AVRILOS SysTick module

avr16_v123_CodeProj.zip
- avr16_v123_CodeProj
  - build.dep
    - adc.P
    - applic.P
    - dbgext.P
    - debugger.P
    - delay.P
    - kernel.P
    - serapp.P
    - Timer0.P
    - typeconv.P
    - Uart.P
  - build.err
  - build.lst
    - adc.lst
    - applic.lst
    - dbgext.lst
    - debugger.lst
    - delay.lst
    - kernel.lst
    - kernel.map
    - serapp.lst
    - Timer0.lst
    - typeconv.lst
    - Uart.lst
  - build.obj
    - adc.o
    - applic.o
    - dbgext.o
    - debugger.o
    - delay.o
    - kernel.elf
    - kernel.o
    - kernel.obj
    - serapp.o
    - Timer0.o
    - typeconv.o
    - Uart.o
  - build.rom
    - kernel.eep
    - kernel.rom
  - cfg
    - compile.in
    - compileflags.in
    - env.in
    - hw.in
    - srcobj.in
    - swdef.in
  - kernel_elf.aps
  - kernel_elf.aws
  - license.txt
  - makefile
  - src
    - applic
      - applic.c
      - applic.h
      - cfg
        
        fpga_cfg.c
        
        fpga_cfg.h
      - fpgassi.c
      - fpgassi.h
      - Kernel.c
      - serapp.c
      - serapp.h
    - debug
    - includes
    - periphext
      - asciitab.h
      - keymat44.c
      - keymat44.h
      - lcm_char.c
      - lcm_char.h
      - lpc.c
      - lpc.h
      - scard.c
      - scard.h
      - sst.c
      - sst.h
      - xcs_cfg.c
      - xcs_cfg.h
    - periphint
      - adc.c
      - adc.h
      - eeprom.c
      - eeprom.h
      - Motor.c
      - Motor.h
      - spi.c
      - spi.h
      - Timer0.c
      - Timer0.h
      - Timer1.c
      - Timer1.h
      - Uart.c
      - Uart.h
    - Utils
      - delay.c
      - delay.h
      - typeconv.c
      - typeconv.h

/***************************************************************************
 Project:		AVRILOS
 Title:			Settings for Hardware &	Software
 Author:		Ilias Alexopoulos
 Version:		2.00
 Last updated:	28-Oct-2010
 Target:		AT90S8535/ATMEGA163
 File:			settings.h

* Support E-mail:
* avrilos@ilialex.gr
* 
* V2.00     28-Oct-2010     Initial AVRILOS Release
* V2.01     25-Apr-2011     Modifications to control FPGA & Motor
*
* license: See license.txt on root directory (CDDL)
*

* DESCRIPTION
* Global Header File
***************************************************************************/


#include "legacy.h"

#define c_VEROSSTR "\nAVRILOS " XSTR(c_VEROS)" started...\r\n"
#define c_VERAPPSTR "APP Version " XSTR(c_VERAPP)"\r\n"

/***********************************
	Modules Included in Program
	Undef unneeded modules
***********************************/

/* Defines set from makefile */
/* These are here just for reference */
//#define MOD_SYSTIMER_ON
//#define MOD_UART_ON
//#define MOD_ADC8_ON
//#define MOD_DEBUGGER_ON
//#define MOD_FPGAXCS_ON
//#define MOD_LCMCHAR_ON
//#define MOD_KEY44_ON
//#define MOD_LPC_ON
//#define MOD_SERAPP_ON
//#define MOD_SPI_ON
//#define MOD_MOTORTIMER_ON


// CPU Definitions must match makefile (swdef.in)
#define c_AT90S8515			0
#define c_ATMEGA16 		    1
#define c_ATMEGA163 			2
#define c_ATMEGA164P 		3
#define c_ATMEGA323 			4

/**************** Serial Port (UART) ****************/
/* set baud rate here if not in makefile 			*/
//#define UART_BAUD_RATE 		19200

/**************** Timer 0 ***************************/
/* System Tick 										*/
/* if not set in makefile				*/
//#define	c_SysTickPeriod_ms	500

/* Hardware Defined Constant */
/* Defined in makefile  */
//#define MPUCLK_Hz        	8000000               /* 4MHz processor */


/* Select Port and bit for LED Alive */
#define	b_LedAlive		4	
#define	c_PORTALIVE		PORTB
#define	c_DDRPALIVE		DDRB

/******************** Pump Control *****************/
#define c_LEDPIN            PINC
#define c_LEDPORT           PORTC
#define c_LEDDDR            DDRC

#define c_TRGPIN            PINB
#define	c_TRGPORT			PORTB
#define	c_TRGDDR			DDRB

#define c_GPPIN             PINA
#define	c_GPPORT			PORTA
#define	c_GPDDR			    DDRA


// Port B
#define b_Trig      3
// Port A
#define b_Pump      0
#define b_Bypass    5

#define c_ADC_CHLDR		5 // Channel 5

// Port C
#define b_LedYel  	7
#define b_LedRed 		5
#define b_LedGrn   	4


/**************** FPGA Configuration I/O ***********/
#define	c_CFGPIN			PINB
#define	c_CFGPORT			PORTB
#define	c_CFGDDR			DDRB

/* for Spartan/XL, XC4000 */
#define	b_Init			3 
#define	b_Prog		    2

/* Used with SPI */
#define	b_Din			5		/* MOSI for SPI instead of MISO (6) */
#define	b_CClk			7

/* old definitions for XC3000 */
#define	b_Reset 		b_Prog
#define	b_Done 			b_Init

/**************** FPGA Application I/O *************/

#define	c_IFCPIN			PIND
#define	c_IFCPORT			PORTD
#define	c_IFCDDR			DDRD

#define	b_MCUClk		7
#define	b_MCUFrame	    6
#define	b_MCUData		3

/**************** LCM ******************************/
#define c_LCMPIN			PINC
#define c_LCMPORT			PORTC
#define c_LCMDDR			DDRC

/* Port C */
#define	b_LCM_RS		PC6
#define b_LCM_RW			PC5
#define b_LCM_E			PC4
#define b_LCM_D7 			PC3
#define b_LCM_D6 			PC2
#define b_LCM_D5 			PC1
#define b_LCM_D4 			PC0

/**************** LPC Bus ****************************/
#define c_LPCPIN				PINC
#define c_LPCPORT			PORTC
#define c_LPCDDR			DDRC
#define c_LPCBDDR			DDRB
#define c_LPCBPORT			PORTB

/* Port B */
#define b_LFRAME			PB1
#define b_LCLK			PB6
/* Port C */
#define b_LAD3 			PC3
#define b_LAD2 			PC2
#define b_LAD1 			PC1
#define b_LAD0 			PC0

/* Used with SPI */
/**************** SPI Configuration I/O ***********/
#define	c_SPIPIN	    	PINB
#define	c_SPIPORT	    	PORTB
#define	c_SPIDDR	    	DDRB

#define	b_SPIMOSI		5		
#define	b_SPIMISO		6
#define	b_SPICLK		7


/*************** UART Buffer Sizes ******************/
#define c_RXBUFLEN	16 // 16
#define c_TXBUFLEN	64  // 16

/**************** PWM ****************************/
#define	c_PWMPIN	    PIND
#define	c_PWMPORT	PORTD
#define	c_PWMDDR		DDRD


#define	b_PWM1			4
#define	b_PWM2			5


/**************** Motor Control ****************************/
#define	c_MOTORPIN	PINC
#define	c_MOTORPORT	PORTC
#define	c_MOTORDDR	DDRC

#define 	c_MOTORA_1	4	
#define 	c_MOTORA_2	5
#define 	c_MOTORB_1	2
#define 	c_MOTORB_2	3


/**************** SCARD ****************************/
#define c_SCARDPIN      		PINC 
#define c_SCARDPORT     	PORTC
#define c_SCARDDDR      	DDRC

#define b_CRST			0		// Card RST
#define b_CCLK			1		// Card Clock
#define b_CDAT			2		// Card Data	
#define b_NCARDIN     	3       // Card inserted


/*************** ADC Channels ******************/
#define c_MAXADCCH 		8

/* Possible settings for Vref - do not change */
#define VREF_AREF		0x00
#define VREF_AVCC		0x40
#define VREF_RESV		0x80
#define VREF_256V		0xC0
/* Data adjustment right/Left */
#define DATA_RADJ		0x00
#define DATA_LADJ		0x20
/* reference channels */
#define CHANREF_122V	0x1E
#define CHANREF_GND		0x1F

/* ADC Prescaler */
#define ADCPRSC_2		0x01
#define ADCPRSC_4		0x02
#define ADCPRSC_8		0x03
#define ADCPRSC_16	    0x04
#define ADCPRSC_32	    0x05
#define ADCPRSC_64	    0x06
#define ADCPRSC_128	    0x07

/* selected Setting for Vref */
#define ADC_VREF_MODE	VREF_AREF
#define ADC_DATA_ADJ	DATA_RADJ

/*************** Matrix Keyboard 4x4 ******************/
#define c_ROWDDR		DDRC
#define c_COLDDR		DDRB
#define c_ROWPORT		PORTC
#define c_COLPORT		PORTB
#define c_ROWPIN		PINC
#define c_COLPIN		PINB
#define c_ROWMASK		0x0f
#define c_ROWIMASK		0xf0
#define c_COLMASK		0xf0
#define c_COLIMASK		0x0f
#define c_NOKEY			0xff

#define c_KEYBUFSIZE	4
#define c_KEYDEBLIMIT	3

/*************** SysStat Register ******************/
#define b_SysTick				0
#define b_DBG					1
#define b_AppTick				2
#define b_ADCTick				3
#define b_LCDBusy				4



/*************** StatReg Register ******************/
#define b_FPGACfg	0


/*****************************************/
/* Firmware Settings */
#define PRSC1              1
#define PRSC1_SELECT       1               /* divide by 1 */

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License

This article, along with any associated source code and files, is licensed under The Common Development and Distribution License (CDDL)

Written By

grilialex

Systems Engineer AI ZeroCaliber Ltd

Cyprus

More than 15 year of Embedded Systems development designing both hardware & software.
Experience with Product Development,lab prototypes and Automated Testers, Sensors, motors and System Engineering. Have used numerous micro-controllers/processors, DSP & FPGAs.

Please check AI ZeroCaliber if you need any help.
You may find also my personal site: Ilialex and my blog site: Ilialex Blog

AVRILOS SysTick Timer enhancements

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