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Hello everyone I've wriiten a VHDL code for my project. It's a clock divider code. The input clock is 12MHz and output clocks are 500KHz and 9.6KHz. I want to simulate it but I don't know how to write a testbench code. Can anyone please help me!!!
Thank you.
The code which I have written is:-
library IEEE;
entity clk_gen is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_serial : inout STD_LOGIC;
clk_pwm : inout STD_LOGIC);
end clk_gen;

architecture Behavioral of clk_gen is

signal counter_serial: integer range 0 to 3000 := 0;
signal counter_pwm: integer range 0 to 100 := 0;


clk_gen_process: process(clk, reset)

if (reset = '0') then
clk_serial <= '0';
clk_pwm <= '0';
counter_serial <= 0;
counter_pwm <= 0;
elsif (clk'event and clk = '1') then
if (counter_serial < 625) then -- Baud Rate Generation (12000000/9600/2)
counter_serial <= counter_serial + 1;
counter_serial <= 0;
clk_serial <= not(clk_serial);
end if;

if (counter_pwm < 11) then -- 500 kHz clk generation
counter_pwm <= counter_pwm + 1;
counter_pwm <= 0;
clk_pwm <= not(clk_pwm);
end if;
end if;
end process;
end Behavioral;

What I have tried:

I've written the code for frequency divider but I'm unable to simulate it because I don't know hoe to write a testbench. I'm new to VHDL and I'm in learning phase. Please help!!!

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