How to add delays in between states in a VHDL code..?

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VHDL

I am creating a code for Traffic light control. I have developed the code as given below. I need to add a delay of 10s between the states, but I don't have any idea of doing it. I have already defined time 'T' as a standard logic vector but this cannot be used to add the timing. I am going to implement this in a Xilinx Nanoboard 3000 with a clock speed of 20MHz. Can I use the clock speed to generate the delays..?? What variables should I include into the code instead of 'T', and where should I put them?

What I have tried:

entity FSM_for_Traffic_Lights is
port ( Reset, CLK : in std_logic;
T : in integer range 4 downto 0;
LG, LY, LR : out std_logic );
end entity FSM_for_Traffic_Lights ;

Architecture behaviour of FSM_for_Traffic_Lights is
Type statetype is (s_r, s_ry, s_g, s_y);
Signal CurState, NxtState: statetype:= s_r;

NSL: process (CurState, T)
begin
case CurState is
when s_r =>
if (T = 1) then
NxtState <= s_ry;
end if;
when s_ry =>
if (T = 2) then
NxtState <= s_g;
end if;
when s_g =>
if (T = 3) then
NxtState <= s_y;
end if;
when s_y =>
if ( T = 4) then
NxtState <= s_r;
end if;
end case;
end process;

SM: process (CLK, Reset)
begin
if Reset=’1’ then
CurState <= s_r;
elsif rising_edge (CLK) then
CurState <= NxtState;
end if;
end process;

OL: process (CurState)
begin
if CurState = s_r then
LG <= ’0’; LY <= ’0’; LR <= ’1’;
elsif CurState = s_yr then
LG <= ’0’; LY <= ’1’; LR <= ’1’;
elsif CurState = s_g then
LG <= ’1’; LY <= ’0’; LR <= ’0’;
elsif CurState = s_y then
LG <= ’0’; LY <= ’1’; LR <= ’0’;
end if;
end process;