I implemented a simple up counter using modelsim .the code is in verilog.

See more:

Verilog

module up_counter    (
output reg [7:0] out     ,  // Output of the counter
input  wire      enable  ,  // enable for counter
input  wire      clk     ,  // clock Input
input  wire      reset      // reset Input
);
//-------------Code Starts Here-------
always_ff @(posedge clk)
if (reset) begin
  out <= 8'b0 ;
end else if (enable) begin
  out ++;
end

endmodule

thats the code.

What I have tried:

the first time i ran it in modelsim it worked fine. being new to this software,i am unable to figure out whats the problem.to implement,i first, clocked the clk signal and then forced the enable to 1 and reset to zero.moreover, i also set the output at zero.but after running the code,it remains at zero only.
please help.