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Hello everybody.
I want to write code for a 16-bit register with parallel load / shift_R / shift_L / asynchronous_reset.
I have already written the code(below) ,but I have no idea if it's correct.I want your help !!!
I have an examination in a few days...

// 16-bit register -> asynchronous reset && parallel loading of D[0...15] inputs && right and left shift with serial input SI


What I have tried:

entity register_16 is
port(D_in : in std_logic_vector(15 downto 0); D_out : out std_logic_vector(15 downto 0); CLK , CLR , S1 , S0 : in std_logic );
end entity register_16;

architecture behave of register_16 is
process(CLK , CLR , S)
if(CLR = '0') then -- asynchronous reset
D_out <= (D_out'range => '0');

elsif(CLK = '1' and CLK'event) then -- parallel load S1S0 => 00
if( (not S1 and not S0) = '1') then
D_out <= D_in;

elsif((not S1 and S0) = '1') then -- shift right S1S0 => 01
for i in 15 downto 1 loop
D_out(i - 1) <= D_in(i);
end loop;

elsif( (S1 and not S0) = '1') then -- shift left S1S0 => 10
for i in 0 downto 14 loop
D_out(i + 1) <= D_in(i);
end loop;
end if;
end if;
end process;
end behave;
Updated 1-Sep-20 3:15am

1 solution

So run it through a simulator: Google - VHDL Simulator[^]
How did you think it's done in the real world?
Richard MacCutchan 1-Sep-20 9:34am
I use a pentagram and a few choice incantations. :)
OriginalGriff 1-Sep-20 10:28am
I tried that a couple of decades ago - then farmed it out to people who knew what they were doing (and who laid out the Arm processor and FPGA on a tiny PCB ...) :D
Nick_is_asking 1-Sep-20 10:30am

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