15,749,352 members

See more:

So I need some help I need to write design and testbench file for VHDL.

It is interleaver for 4x4 matrix, I've got input speed 10 Mbs and clock 10 Mhz. The output is a sequence 10 Mbs with also clock speed 10 Mhz. The output of interleaver should appear after it recives all 16 bits. The sequence is:

{1101 1110 1011 1010}

Output sequnce is:

{1111 1100 0111 1010}

Thank you for your help.

So I think i got the design right and now in pursuit trying to make the testbench file:

**What I have tried:**

<pre>

I am bachelor of Information technology and just practicing some VHDL which I got from friends studyng Electrical engineering as I didn't had much of VHDL programming. This was one of their assigments so I got stuck with this one.

Honestly I am just a begginer and don't really get what to do I am just stuck in this one and any help would be great.

It is interleaver for 4x4 matrix, I've got input speed 10 Mbs and clock 10 Mhz. The output is a sequence 10 Mbs with also clock speed 10 Mhz. The output of interleaver should appear after it recives all 16 bits. The sequence is:

{1101 1110 1011 1010}

Output sequnce is:

{1111 1100 0111 1010}

Thank you for your help.

So I think i got the design right and now in pursuit trying to make the testbench file:

<pre>

I am bachelor of Information technology and just practicing some VHDL which I got from friends studyng Electrical engineering as I didn't had much of VHDL programming. This was one of their assigments so I got stuck with this one.

Honestly I am just a begginer and don't really get what to do I am just stuck in this one and any help would be great.

Comments

If you are a beginner then maybe this will help: VHDL Tutorial - Introduction to VHDL for beginners[^].

Permalink

Share this answer

Quote:I am bachelor of Information technology and just practicing some VHDL which I got from friends studyng Electrical engineering as I didn't had much of VHDL programming. This was one of their assigments so I got stuck with this one.

So it's someone else's homework that you can't do ... still homework.

We are more than willing to help those that are stuck: but that doesn't mean that we are here to do it all for you! We can't do all the work, you are either getting paid for this, or it's part of your grades and it wouldn't be at all fair for us to do it all for you.

So we need you to do the work, and we will help you when you get stuck. That doesn't mean we will give you a step by step solution you can hand in!

Start by explaining where you are at the moment, and what the next step in the process is. Then tell us what you have tried to get that next step working, and what happened when you did.

If you are having problems getting started at all, then this may help: How to Write Code to Solve a Problem, A Beginner's Guide[^]

Permalink

Share this answer

Comments

JustBeginnerVHDL
7-May-21 4:43am

Ok, I am not trying to get any money or any kind of doing others work for them at least I got the ethics part in IT learnt the right way. I tried with this question on Stackoverflow but it got it reputeion right not very friendly for begginers unfortunatly. This was actually their HW which already expired and had to be submited. I generaly have problem with clocks and speed implementation in VHDL. The solution I have found is using FPGA chipset and setting the clocks there or defining the signal time and using it at testbench part with "wait for" command but still there is the speed of 10 Mbs which I really dont get how to solve.

I am really greatfull for answearing and showing any interest for the question.

I am really greatfull for answearing and showing any interest for the question.

OriginalGriff
7-May-21 4:58am

The ethics question is "why are you doing someones else's homework for them?":

Quote:"I got from friends studyng Electrical engineering as I didn't had much of VHDL programming. This was one of their assigments so I got stuck with this one."

And we - and SO - aren't here to do homework for people, regardless of whether they get "paid" for it or not!

Plus, you'd be amazed how many people try the "it's for a friend, not me so it's OK for you to do all the work" gambit on us ... :sigh:

Quote:"I got from friends studyng Electrical engineering as I didn't had much of VHDL programming. This was one of their assigments so I got stuck with this one."

And we - and SO - aren't here to do homework for people, regardless of whether they get "paid" for it or not!

Plus, you'd be amazed how many people try the "it's for a friend, not me so it's OK for you to do all the work" gambit on us ... :sigh:

JustBeginnerVHDL
7-May-21 5:17am

So ok I get that you see all kinds of kind of questions, but the assigment is already done and had to be submited at the and of last month. I am not trying to argue or trying to make you believe in something.

I am here as someone who is begginer and trying to develop myself. I can see from your profile that you have got a lot of experience but I dont get why is hard to help someone who is really a starter and just asking for opinion how something can be solved. And again thank you for your time.

I am here as someone who is begginer and trying to develop myself. I can see from your profile that you have got a lot of experience but I dont get why is hard to help someone who is really a starter and just asking for opinion how something can be solved. And again thank you for your time.

So just to give an update I have managed to resolve this actually I have kind of forgot the matrix transpose.... :embarrassed:

Here is my solution:

making package using arrays as followed:

then the design part:

and finally tb part:

Here is my solution:

making package using arrays as followed:

package newtype is type row_1 is array(0 to 3) of integer; type matrix_inter is array(0 to 3, 0 to 3) of integer; end newtype;

then the design part:

entity test is port(input: in matrix_inter; clk: in std_logic); end test; architecture arch of test is signal matrix : matrix_intert; signal temp_row : row_1; signal count : unsigned(1 downto 0) := "0"; function extract_row( m : matrix_inter; row : integer) return row_1 is variable ret : row_1; begin for i in row_1'range loop ret(i) := m(row, i); end loop; return ret; end function; begin process(clk) begin if rising_edge(clk) then temp_row <= extract_row( matrix, to_integer(count) ); count <= count + 1; end if; end process; end arch;

and finally tb part:

entity test is port(input: in matrix_inter; clk: in std_logic); end test; architecture arch of test is signal matrix : matrix_inter; signal temp_row : row_1; signal count : unsigned(1 downto 0) := "0"; function extract_row( m : matrix_inter; row : integer) return row_1 is variable ret : row_1; begin for i in row_1'range loop ret(i) := m(row, i); end loop; return ret; end function; begin process(clk) begin if rising_edge(clk) then temp_row <= extract_row( matrix, to_integer(count) ); count <= count + 1; end if; end process; end arch;

Permalink

Share this answer

Comments

JustBeginnerVHDL
7-May-21 17:39pm

Now theres only left to figure out speed and delay clock.

This content, along with any associated source code and files, is licensed under The Code Project Open License (CPOL)

CodeProject,
20 Bay Street, 11th Floor Toronto, Ontario, Canada M5J 2N8
+1 (416) 849-8900

Thank you for being so kind and willing to help.