PIC24 UART # 3 Refuses 5th Byte

The chip in question is PIC24FJ256GB210

We have an embedded system with two of your microprocessors.

The two microprocessors use UART #3 to communicate.

I place 4 bytes into UART #3. The 5th byte will not go in.

My local hardware expert says that if I turn off flow control that the bytes will go out no matter what.

Is this true ? I've never heard that one before. I thought it was a hardware signal on the other side; i.e., a read signal has to occur on the other side; after which the FIFO buffer re-rigs the innards and the guy on the first side can start stuffing again (well, one for one under these circumstances; but whatever; a read on the other side will let me write on this one; I thought).

His definition of "turn off flow control" is for me to not use PPS (Peripheral Pin Select) to map either the RTS (Request to Send) or CTS (Clear To Send) pins to their corresponding physical pin on the board.

I did that.

Result: no change; that is to say, the 4-Byte FIFO buffer fills up.

Will disabling CTS and RTS let me push bytes in with abandon ?

Tags: PIC