Convert Xilinx FPGA/CPLD to C Source

--------------------------------------------------------------------------------------------
-- Company     : ILIALEX RESEARCH LAB
-- Project     : AVR & FPGA Control
-- Proj. Code  : HDL-IOSS0002ILX
-- Title       : Synchronous Serial Interface
-- Description : SSI Interface to external microprocessor
-- File        : ssi.vhd
-- Type        : VHDL
-- Library     : IRL - VHDL, Project Lib
-- Author      : Alexopoulos Ilias
-- Comments    :
--
-- Dependencies:
--
-- Revisions   :
-- Version     : (Version) (dd/mm/yy) 	changes
--			        0.00	11/5/2002 	First implementation
--					1.00	03/04/2011	Initial Release
--                  
-- 
-- license: See license.txt on root directory (CPOL)
--
-- Generics:
--        maxdecode : Registers Selects to access
--        maxaddr   : Maximum Address bits (MSB)
--
-- Inputs:
--        rstb      : Master Reset (Xilinx GSR block)
--        Clk		: System Clock, preferred to be 8MHz for correct Servo Timing
--        MCUClk	: Asynchronous Clk from Master
--        MCUFrame	: Frame from Master
--        mcudatin	: Serial Data Input
--        pdatain   : Register Parallel In
--
-- Outputs:
--
--        pdataout  : Register Parallel Out
--        sel       : Register select
--        pwr       : Write enable (parallel bus) to register
--        prd       : Read enable (parallel bus) from register
--        mcudataen : Serial Data Enable 
--        mcudataout: Serial Data Output
--
--
--
--
-- Notes on design:
--
-- Support E-mail: avrilos@ilialex.gr
-- license: See license.txt on root directory (CPOL)
--------------------------------------------------------------------------------------------


LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY ssi IS
	GENERIC (
		maxdecode: integer := 25;
		maxaddr:   integer := 4
		);
    PORT (
    	rstb: 		IN std_logic;
        clk:		IN std_logic;
        mcuclk: 	IN std_logic;
        mcuframe: 	IN std_logic;
        mcudatin: 	IN std_logic;

        pdatain:	IN std_logic_vector(7 DOWNTO 0);

        pdataout:	OUT std_logic_vector(7 DOWNTO 0);
        --paddr:		OUT std_logic_vector(3 DOWNTO 0);
        sel:		OUT std_logic_vector(maxdecode DOWNTO 0);
        pwr:		OUT std_logic;
        prd:		OUT std_logic;
        mcudataen:	OUT std_logic;
        mcudatout:	OUT std_logic

    );
END ssi;

ARCHITECTURE rtl OF ssi IS

----------------------------- Component declaration
COMPONENT ssisync
    PORT (
    	rstb: 			IN std_logic;
        clk:			IN std_logic;
        ext_mcuclk: 	IN std_logic;
        ext_mcuframe: 	IN std_logic;
        ext_mcudatin: 	IN std_logic;

		mcuclk_en: 		OUT std_logic;
        mcuframe: 		OUT std_logic;
        mcudatin: 		OUT std_logic

    );
END COMPONENT;

COMPONENT ssibitcnt
    PORT (
    	rstb: 		IN std_logic;
        clk:		IN std_logic;

        mcuclk_en: 	IN std_logic;
        start: 		IN std_logic;

        bitcnt: 	OUT std_logic_vector(4 DOWNTO 0)

    );
END COMPONENT;

COMPONENT ssifsm
    GENERIC(
    	caddr_size:	integer;
    	cdata_size:	integer
    );
    PORT (
    	rstb: 		IN std_logic;
        clk:		IN std_logic;

        mcuframe: 	IN std_logic;
		bitcnt:		IN std_logic_vector(4 DOWNTO 0);
		dir_rd:		IN std_logic;
		
        addr_shift:	OUT std_logic;
        data_shift:	OUT std_logic;
        data_rd:	OUT std_logic;
        data_wr:	OUT std_logic;
        sdout_en:	OUT std_logic

    );
END COMPONENT;

-- Component ssishifter
COMPONENT ssishifter
    PORT (
    	rstb: 		IN std_logic;
        clk:		IN std_logic;

		mcuclk_en: 	IN std_logic;
        mcudatin: 	IN std_logic;

        addr_shift:	IN std_logic;
        data_shift: IN std_logic;
        pdata_in:	IN std_logic_vector(7 DOWNTO 0);
        
		addr:		OUT std_logic_vector(7 DOWNTO 0);
		pdata_out:	OUT std_logic_vector(7 DOWNTO 0);
		mcudatout: 	OUT std_logic
	);
END COMPONENT;

-- component ssidecoder
COMPONENT ssidecoder
	GENERIC (
		maxdecodebit: 	integer;
		maxaddrbit:	integer
	);
    PORT (
    	rstb: 		IN std_logic;
        clk:		IN std_logic;

		prd:	 	IN std_logic;
        paddr: 		IN std_logic_vector(maxaddrbit DOWNTO 0);

        sel:		OUT std_logic_vector(maxdecodebit DOWNTO 0)

    );
END COMPONENT;

------------------------ Component Signals

-- Component: ssisync
SIGNAL ssisync_rstb: 			std_logic;
SIGNAL ssisync_clk:				std_logic;
SIGNAL ssisync_ext_mcuclk: 		std_logic;
SIGNAL ssisync_ext_mcuframe: 	std_logic;
SIGNAL ssisync_ext_mcudatin: 	std_logic;

SIGNAL ssisync_mcuclk_en: 		std_logic;
SIGNAL ssisync_mcuframe: 		std_logic;
SIGNAL ssisync_mcudatin: 		std_logic;


-- Component: ssibitcnt
SIGNAL ssibitcnt_rstb: 			std_logic;
SIGNAL ssibitcnt_clk:			std_logic;
SIGNAL ssibitcnt_mcuclk_en: 	std_logic;
SIGNAL ssibitcnt_start: 		std_logic;
SIGNAL ssibitcnt_bitcnt:		std_logic_vector(4 DOWNTO 0);

-- Component ssifsm
SIGNAL ssifsm_rstb: 			std_logic;
SIGNAL ssifsm_clk:				std_logic;
SIGNAL ssifsm_mcuframe: 		std_logic;
SIGNAL ssifsm_dirbit_rd:		std_logic;
SIGNAL ssifsm_addr_ok: 			std_logic;
SIGNAL ssifsm_data_ok: 			std_logic;
SIGNAL ssifsm_bitcnt:			std_logic_vector(4 DOWNTO 0);

SIGNAL ssifsm_start: 			std_logic;
SIGNAL ssifsm_addr_shift:		std_logic;
SIGNAL ssifsm_data_shift:		std_logic;
SIGNAL ssifsm_data_rd:			std_logic;
SIGNAL ssifsm_data_wr:			std_logic;
SIGNAL ssifsm_sdout_en:			std_logic;
SIGNAL ssifsm_paddr_en:			std_logic;

-- Component ssishifter
SIGNAL ssishifter_rstb: 		std_logic;
SIGNAL ssishifter_clk:			std_logic;

SIGNAL ssishifter_mcuclk_en: 	std_logic;
SIGNAL ssishifter_mcudatin: 	std_logic;

SIGNAL ssishifter_addr_shift:	std_logic;
SIGNAL ssishifter_data_shift: 	std_logic;
--SIGNAL ssishifter_data_rd:		std_logic;
SIGNAL ssishifter_pdata_in:		std_logic_vector(7 DOWNTO 0);

SIGNAL ssishifter_dirbit_rd:	std_logic;
SIGNAL ssishifter_addr:			std_logic_vector(7 DOWNTO 0);
SIGNAL ssishifter_pdata_out:	std_logic_vector(7 DOWNTO 0);
SIGNAL ssishifter_mcudatout: 	std_logic;

-- decoder
SIGNAL ssidecoder_rstb: 		std_logic;
SIGNAL ssidecoder_clk:			std_logic;
SIGNAL ssidecoder_prd:			std_logic;
SIGNAL ssidecoder_paddr:		std_logic_vector(maxaddr DOWNTO 0);

SIGNAL ssidecoder_sel:			std_logic_vector(maxdecode DOWNTO 0);

------------------------ Internal Signals

SIGNAL detclk:					std_logic;

SIGNAL mcuclk_en_sig:			std_logic;
SIGNAL mcuframe_sig	:           std_logic;
SIGNAL mcudatin_sig	:           std_logic;

BEGIN

issifsm: ssifsm
GENERIC MAP (
	caddr_size	=> 8,
	cdata_size	=> 8
)
PORT MAP
(
	rstb 	      => ssifsm_rstb,
	clk           => ssifsm_clk,

	mcuframe      => ssifsm_mcuframe,
	bitcnt 	  	  => ssifsm_bitcnt,
	dir_rd	      => ssifsm_dirbit_rd,
	
	addr_shift    => ssifsm_addr_shift,
	data_shift    => ssifsm_data_shift,
	data_rd	      => ssifsm_data_rd,
	data_wr	      => ssifsm_data_wr,
	sdout_en	  => ssifsm_sdout_en
);

issishifter: ssishifter
PORT MAP
(
	rstb      		=> ssishifter_rstb,
	clk       		=> ssishifter_clk,

	mcuclk_en 		=> ssishifter_mcuclk_en,
	mcudatin  		=> ssishifter_mcudatin,

	addr_shift		=> ssishifter_addr_shift,
	data_shift		=> ssishifter_data_shift,
	pdata_in  		=> ssishifter_pdata_in,

	--dirbit_rd 		=> ssishifter_dirbit_rd,
	addr      		=> ssishifter_addr,
	pdata_out 		=> ssishifter_pdata_out,
	mcudatout 		=> ssishifter_mcudatout

);

issibitcnt:	ssibitcnt
PORT MAP
(
	rstb	   		=> ssibitcnt_rstb,
	clk        		=> ssibitcnt_clk,
	mcuclk_en  		=> ssibitcnt_mcuclk_en,
	start      		=> ssibitcnt_start,
	bitcnt			=> ssibitcnt_bitcnt
);

issisync: ssisync
PORT MAP
(
	rstb        	=> ssisync_rstb,
	clk				=> ssisync_clk,
	ext_mcuclk		=> ssisync_ext_mcuclk,
	ext_mcuframe	=> ssisync_ext_mcuframe,
	ext_mcudatin	=> ssisync_ext_mcudatin,

	mcuclk_en 		=> ssisync_mcuclk_en,
	mcuframe 		=> ssisync_mcuframe,
	mcudatin    	=> ssisync_mcudatin

);

issidecoder: ssidecoder
GENERIC MAP (
	maxdecodebit		=> maxdecode,
	maxaddrbit			=> maxaddr
)
PORT MAP
(
	rstb			=> ssidecoder_rstb,
	clk				=> ssidecoder_clk,
	prd				=> ssidecoder_prd,
	paddr			=> ssidecoder_paddr,

	sel				=> ssidecoder_sel
);



-------------------------------------------
-- global signals
ssisync_rstb 			<= rstb;
ssibitcnt_rstb 			<= rstb;
ssifsm_rstb 			<= rstb;
ssishifter_rstb 		<= rstb;
ssidecoder_rstb			<= rstb;


ssisync_clk				<= clk;
ssibitcnt_clk			<= clk;
ssifsm_clk				<= clk;
ssishifter_clk			<= clk;
ssidecoder_clk			<= clk;

-- ssisync inputs
ssisync_ext_mcuclk 		<= mcuclk;
ssisync_ext_mcuframe 	<= mcuframe;
ssisync_ext_mcudatin 	<= mcudatin;

-- ssisync outputs
mcuframe_sig			<= ssisync_mcuframe;
mcudatin_sig			<= ssisync_mcudatin;

-- bitcnt inputs
ssibitcnt_mcuclk_en		<= ssisync_mcuclk_en;

ssibitcnt_start			<= ssisync_mcuframe;

-- fsm inputs / shifter
ssishifter_dirbit_rd	<= ssishifter_addr(7);

ssifsm_mcuframe			<= mcuframe_sig;
ssifsm_dirbit_rd		<= ssishifter_dirbit_rd;
ssifsm_bitcnt			<= ssibitcnt_bitcnt;

-- fsm inputs / bitcnt outputs



-- shifter inputs
ssishifter_mcuclk_en	<= ssisync_mcuclk_en;
ssishifter_mcudatin		<= mcudatin_sig;

ssishifter_addr_shift	<= ssifsm_addr_shift;
ssishifter_data_shift	<= ssifsm_data_shift;
--ssishifter_data_rd		<= ssifsm_data_rd;


-- SSI outputs
ssishifter_pdata_in		<= pdatain;

-- shifter outputs
pdataout				<= ssishifter_pdata_out;
--paddr					<= ssishifter_addr(maxaddr DOWNTO 0);
mcudatout				<= ssishifter_mcudatout;

-- fsm outputs
pwr						<= ssifsm_data_wr;
prd						<= ssifsm_data_rd;
mcudataen				<= ssifsm_sdout_en;

-- decoder input/outputs
ssidecoder_prd			<= ssifsm_addr_shift OR ssifsm_data_wr; --ssifsm_paddr_en;
ssidecoder_paddr		<= ssishifter_addr(ssidecoder_paddr'RANGE);

--sel						<= ssidecoder_sel(maxdec DOWNTO 0);
sel						<= ssidecoder_sel(maxdecode DOWNTO 0);


END rtl;