Convert Xilinx FPGA/CPLD to C Source

--------------------------------------------------------------------------------------------
-- Company     : ILIALEX RESEARCH LAB
-- Project     : Multi-Channel RC Servo Control
-- Proj. Code  : HDL-IOSS0002ILX
-- Title       : AVRILOS Package for Constants
-- Description : 
-- File        : avrilos_pkg.vhd
-- Type        : VHDL
-- Library     : IRL - VHDL, Project Lib
-- Author      : Alexopoulos Ilias
-- Comments    :
--
-- Dependencies:
--
-- Revisions   :
-- Version     : (Version) (dd/mm/yy) 	changes
--			        0.00	11/05/2002 	First implementation
--					1.00	03/04/2011	Initial Release
--                  
--  
--
-- Support E-mail: avrilos@ilialex.gr
-- license: See license.txt on root directory (CPOL)
--------------------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;


PACKAGE avrilos_pkg IS

CONSTANT cMaxChan:			integer := 8;

CONSTANT cMaxAddr:			integer := 4;
CONSTANT cMaxRegs:			integer := 10;
CONSTANT cADDR_FQBASE:		integer := 0;
CONSTANT cADDR_PWMBASE:		integer := 1;
CONSTANT cADDR_LDBASE:		integer := 9;

CONSTANT cFrSize:			integer := 6;
CONSTANT cPWMSize:			integer := 8;
CONSTANT cLdSize:			integer := 4+2;

CONSTANT REG_FREQ:			integer := 0;
CONSTANT REG_DC0:			integer := 1;
CONSTANT REG_DC1:			integer := 2;
CONSTANT REG_DC2:			integer := 3;
CONSTANT REG_DC3:			integer := 4;
CONSTANT REG_DC4:			integer := 5;
CONSTANT REG_DC5:			integer := 6;
CONSTANT REG_DC6:			integer := 7;
CONSTANT REG_DC7:			integer := 8;

CONSTANT REG_LED:			integer := 9;


TYPE type_dutycyc IS ARRAY (integer RANGE cMaxChan-1 DOWNTO 0) OF std_logic_vector(cPWMSize-1 DOWNTO 0);

TYPE type_addr_reg IS ARRAY (integer RANGE 0 TO cMaxRegs-1) OF integer;

CONSTANT addr_reg:	type_addr_reg := (
		REG_FREQ,
		REG_DC0,
		REG_DC1,
		REG_DC2,
		REG_DC3,
		REG_DC4,
		REG_DC5,
		REG_DC6,
		REG_DC7,
		REG_LED	);


END avrilos_pkg;

PACKAGE BODY avrilos_pkg IS

END avrilos_pkg;