Convert Xilinx FPGA/CPLD to C Source

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-- Company     : ILIALEX RESEARCH LAB
-- Project     : AVRILOS FPGA
-- Proj. Code  : HDL-IOSS0002ILX
-- Title       : Serial Synchronous Interface, SSIBITCNT
-- Description : SSI Bit counter in order to dermine when to do various ops.
-- File        : ssibitcnt.vhd
-- Type        : VHDL
-- Library     : IRL - VHDL, Project Lib
-- Author      : Alexopoulos Ilias
-- Comments    :
--
-- Dependencies:
--
-- Revisions   :
-- Version     : (Version) (dd/mm/yy) changes
--					0.00	11/5/2002 	First implementation
--					1.00    01/03/2010  Added documentation for AVRILOS
--
-- Generic:
--
-- Inputs:
--		rstb			: Reset (bar), negative active
--      Clk				: System Clock
--      MCUClk_En		: Pulse (1 system clock) on rising edge of Ext_MCUClk
--		start			: signal to enable counting in bitcnt. Stop counting on end or MCUFrame off.
--
-- Outputs:
--
--		addr_ok			: Address ready to capture (valid)
--		data_ok			: Data from MOSI ready to be used
--
--
--
--
-- Notes on design:
--
-- Support E-mail: avrilos@ilialex.gr
-- license: See license.txt on root directory (CPOL)
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LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY ssibitcnt IS
    PORT (
    	rstb: 		IN std_logic;
        clk:		IN std_logic;

        mcuclk_en: 	IN std_logic;
        start: 		IN std_logic;

        bitcnt: 	OUT std_logic_vector(4 DOWNTO 0)

    );
END ssibitcnt;

ARCHITECTURE rtl OF ssibitcnt IS

SIGNAL bitcnt_sig:		unsigned(bitcnt'range);
SIGNAL clk_en:			std_logic;

BEGIN

clk_en	<= mcuclk_en;

PROCESS(rstb, clk)
BEGIN
	IF rstb = '0' THEN
		bitcnt_sig 			<= (OTHERS => '0');
	ELSIF rising_edge(clk) THEN

		IF start = '1' THEN
				
			IF clk_en = '1' THEN
				IF bitcnt_sig = 16 THEN
				ELSE
					bitcnt_sig <= bitcnt_sig + 1;
				END IF;
			END IF;
		ELSE
			bitcnt_sig	 		<= (OTHERS => '0');
		END IF;

	END IF;

END PROCESS;

bitcnt <= std_logic_vector(bitcnt_sig);

END rtl;