Convert Xilinx FPGA/CPLD to C Source

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-- Company     : ILIALEX RESEARCH LAB
-- Project     : AVRILOS FPGA
-- Proj. Code  : HDL-ICUS00__ILX
-- Title       : Serial Synchronous Interface, SSISHIFTER
-- Description : SSI bit shifter for command & data
-- File        : ssishifter.vhd
-- Type        : VHDL
-- Library     : IRL - VHDL, Project Lib
-- Author      : Alexopoulos Ilias
-- Comments    :
--
-- Dependencies:
--
-- Revisions   :
-- Version     : (Version) (dd/mm/yy) changes
--					0.00	11/05/2002 	First implementation
--					1.00    01/03/2010  Added documentation for AVRILOS
--										Modified to control Rd/Wr from MSB instead from LSB
--
-- Generic:
--
-- Inputs:
--		rstb			: Reset (bar), negative active
--      Clk				: System Clock
--      MCUClk_En		: Pulse (1 system clock) on rising edge of Ext_MCUClk
--      MCUDataIn		: Serial Data Input from MOSI
--		addr_shift		: From FSM, denotes when to enable shift command (addr/rd/wr) from MOSI
--		data_shift		: From FSM, denotes when to enable shift data from MOSI and output to MISO
--		pdata_in		: Parallel data of register to shift-out to MISO, used on read operation
--
-- Outputs:
--
--		addr			: Address of register selected (MSB-1:0)
--		pdata_out		: Data register parallel output to write to register (From MOSI)
--		mcudatout		: Serial output for MISO
--
--
--
--
-- Notes on design:
--		For easier software interface do not change the generic. Although this could provide
--		a somewhat smaller design (maxaddrbit = 5), it would complicate interfacing from project
--		to project. Thus i decided that the penalty of having 8-bits as standard for command/addr
--		it is worth the price and peace of same software functions to always match the hardware.
--		Note that the generic default is overriden by component instantiation (upper layers).
--
-- Support E-mail: avrilos@ilialex.gr
-- license: See license.txt on root directory (CDDL)
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LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY ssishifter IS
    PORT (
    	rstb: 		IN std_logic;
        clk:		IN std_logic;

		mcuclk_en: 	IN std_logic;
        mcudatin: 	IN std_logic;

        addr_shift:	IN std_logic;
        data_shift: IN std_logic;
        pdata_in:	IN std_logic_vector(7 DOWNTO 0);
        
		addr:		OUT std_logic_vector(7 DOWNTO 0);
		pdata_out:	OUT std_logic_vector(7 DOWNTO 0);
		mcudatout: 	OUT std_logic

    );
END ssishifter;

ARCHITECTURE rtl OF ssishifter IS

SIGNAL datashifter:		std_logic_vector(pdata_out'range);
SIGNAL addrshifter:		std_logic_vector(addr'range);

SIGNAL clk_en:			std_logic;
SIGNAL mcudata_out_sig:	std_logic;

BEGIN
	
clk_en	<= mcuclk_en;
	
PROCESS(rstb, clk)
BEGIN
	IF rstb ='0' THEN
		datashifter		<= (OTHERS => '0');
		addrshifter		<= (OTHERS => '0');
		
	ELSIF rising_edge(clk) THEN
	
		-- MCU Clock (SPI/SSI)
		IF clk_en = '1' THEN
			-- Address Phase
			IF addr_shift = '1' THEN
				addrshifter(addrshifter'left DOWNTO 1)	<= addrshifter(addrshifter'left - 1 DOWNTO 0);
				addrshifter(0) 			<= mcudatin;
			END IF;
			
			-- Data Phase	
			IF data_shift = '1' THEN
				datashifter(datashifter'left DOWNTO 1)	<= datashifter(datashifter'left - 1 DOWNTO 0);
				datashifter(0) 			<= mcudatin;
			END IF;
		
		END IF;
		
		-- Register Parallel Load for Read control
		IF addr_shift = '1' THEN 
			datashifter		<= pdata_in;
		END IF;
			
		
	END IF;

END PROCESS;

-- output assignment
mcudata_out_sig		<= datashifter(datashifter'left);
mcudatout			<= mcudata_out_sig;
pdata_out			<= datashifter;
addr				<= addrshifter;

END rtl;