Circuit Engine

Emre Guldogan

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18 Oct 2018GPL355 min read

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A System for Simulation and Analysis of Logic Circuits

circuitengine_-_executable.zip
- CEngine.exe
- Examples
  - 4BitAdder
    - 4bitAdder.cesl
  - 74LS08
    - 74LS08.cec
    - 74LS08.CESL
  - Asynchronous
    - Asynchronous.cec
    - Asynchronous.cesl
  - Dual4InputMux
    - 74153.pdf
    - DUAL4INPUTMUX.cec
    - DUAL4INPUTMUX.CESL
  - ExPage58
    - Page58.cesl
  - FullAdder
    - FullAdder.cec
    - FullAdder.CESL
  - FunctionF
    - FunctionF.cesl
- glut32.dll
- README BEFORE USE.txt
circuitengine_code_files_vs6.0.zip
- Artist.h
- BBNode.h
- Binary.h
- BreadBoard.h
- C.dep
- C.dsp
- C.dsw
- C.mak
- C.ncb
- C.opt
- C.plg
- C.sln
- C.suo
- C.vcproj
- ce.oldmain
- CEngine.cpp
- CEngine.h
- CircuitElement.h
- Debug
  - BuildLog.htm
  - C.pch
  - CEngine.exe
  - CEngine.ilk
  - CEngine.obj
  - CEngine.pdb
  - CEngine.sbr
  - CEngineLog_06.07.04_13.12.40.txt
  - CEngineLog_06.11.04_05.38.39.txt
  - try.cesl
  - vc70.idb
  - vc70.pdb
- Gate.h
- Release
  - 4BitAdder
    - 4bitAdder.cesl
    - CEngineLog_06.10.04_01.26.10.txt
    - CEngineLog_06.25.04_11.13.02.txt
    - CEngineLog_06.25.04_11.13.09.txt
    - CEngineLog_06.30.04_15.40.51.txt
  - 74LS08
    - 74LS08.CESL
    - CEngineLog_06.30.04_15.41.17.txt
  - Async1
    - Async1.cesl
    - ASYNC1~1.cec
    - CEngineLog_06.26.04_13.28.23.txt
    - CEngineLog_06.26.04_13.34.58.txt
    - CEngineLog_06.26.04_13.35.44.txt
    - CEngineLog_06.26.04_13.35.47.txt
    - CEngineLog_07.02.04_00.27.01.txt
  - BuildLog.htm
  - C.pch
  - C.pdb
  - CEngine.exe
  - CEngine.obj
  - DENEME.CESL
  - Dual4InputMux
    - 74153.pdf
    - CEngineLog_06.26.04_13.38.16.txt
    - CEngineLog_06.26.04_13.52.54.txt
    - DUAL4I~1.cec
    - DUAL4INPUTMUX.CESL
  - empty.cesl
  - ExPage58
    - Page58.cesl
  - FF.cesl
  - FullAdder
    - CEngineLog_06.26.04_13.59.41.txt
    - CEngineLog_06.27.04_15.07.48.txt
    - CEngineLog_06.28.04_12.17.08.txt
    - CEngineLog_06.28.04_12.18.36.txt
    - FULLAD~1.cec
    - fULLaDDER.CESL
  - FunctionF
    - CEngineLog_07.02.04_00.26.36.txt
    - FunctionF.cesl
    - InitialScreen.bmp
    - Thumbs.db
  - Many.CESL
  - Page58.cesl
  - SavedLogs
    - CEngineLog_06.26.04_13.17.20.txt
    - CEngineLog_06.26.04_13.21.48.txt
    - CEngineLog_06.26.04_13.21.59.txt
    - CEngineLog_06.26.04_13.23.42.txt
    - CEngineLog_06.26.04_13.23.51.txt
    - CEngineLog_06.26.04_13.31.38.txt
    - CEngineLog_06.28.04_12.15.12.txt
    - CEngineLog_06.28.04_12.15.28.txt
    - CEngineLog_06.30.04_15.39.22.txt
  - try.cesl
  - vc70.idb
cesl_cec_examples.zip
- 4bitAdder.cesl
- CEngineLog_06.10.04_01.26.10.txt
- 74LS08.CESL
- CEngineLog_06.30.04_15.41.17.txt
- Async1
  - Async1.cesl
  - ASYNC1~1.cec
  - CEngineLog_06.26.04_13.28.23.txt
  - 74153.pdf
  - CEngineLog_06.26.04_13.38.16.txt
  - DUAL4I~1.cec
  - DUAL4INPUTMUX.CESL
  - Page58.cesl
  - CEngineLog_06.26.04_13.59.41.txt
  - FULLAD~1.cec
  - fULLaDDER.CESL
  - CEngineLog_07.02.04_00.26.36.txt
  - FunctionF.cesl
glut-3.7.6-bin.zip
- glut-3.7.6-bin
  - glut.def
  - glut.h
  - glut32.dll
  - glut32.lib
  - README-win32.txt
circuitengine_code_files_vs6.0_vs8.0.zip
- Artist.h
- BBNode.h
- Binary.h
- BreadBoard.h
- C.vcproj
- CEngine.cpp
- CEngine.h
- Circuit Engine.sln
- CircuitElement.h
- 4bitAdder.cesl
- 74LS08.CESL
- Async1.cesl
- ASYNC1~1.cec
- Counter.cec
- Counter.cesl
- DUAL4I~1.cec
- DUAL4INPUTMUX.CESL
- FULLAD~1.cec
- fULLaDDER.CESL
- FunctionF.cesl
- Page58.cesl
- try.cesl
- Gate.h
glut-3.spec.zip
- glut-3.spec.pdf
circuitengine_code_files.zip
- Artist.h
- BBNode.h
- Binary.h
- BreadBoard.h
- C.dep
- C.dsp
- C.dsw
- C.mak
- C.ncb
- C.opt
- C.plg
- C.sln
- C.suo
- C.vcproj
- ce.oldmain
- CEngine.cpp
- CEngine.h
- CircuitElement.h
- BuildLog.htm
- C.pch
- CEngine.exe
- CEngine.ilk
- CEngine.obj
- CEngine.pdb
- CEngine.sbr
- CEngineLog_06.07.04_13.12.40.txt
- CEngineLog_06.11.04_05.38.39.txt
- try.cesl
- vc70.idb
- vc70.pdb
- Gate.h
- 4bitAdder.cesl
- CEngineLog_06.10.04_01.26.10.txt
- CEngineLog_06.25.04_11.13.02.txt
- CEngineLog_06.25.04_11.13.09.txt
- CEngineLog_06.30.04_15.40.51.txt
- 74LS08.CESL
- CEngineLog_06.30.04_15.41.17.txt
- Async1.cesl
- ASYNC1~1.cec
- CEngineLog_06.26.04_13.28.23.txt
- CEngineLog_06.26.04_13.34.58.txt
- CEngineLog_06.26.04_13.35.44.txt
- CEngineLog_06.26.04_13.35.47.txt
- CEngineLog_07.02.04_00.27.01.txt
- BuildLog.htm
- C.pch
- C.pdb
- CEngine.exe
- CEngine.obj
- DENEME.CESL
- 74153.pdf
- CEngineLog_06.26.04_13.38.16.txt
- CEngineLog_06.26.04_13.52.54.txt
- DUAL4I~1.cec
- DUAL4INPUTMUX.CESL
- empty.cesl
- Page58.cesl
- FF.cesl
- CEngineLog_06.26.04_13.59.41.txt
- CEngineLog_06.27.04_15.07.48.txt
- CEngineLog_06.28.04_12.17.08.txt
- CEngineLog_06.28.04_12.18.36.txt
- FULLAD~1.cec
- fULLaDDER.CESL
- CEngineLog_07.02.04_00.26.36.txt
- FunctionF.cesl
- InitialScreen.bmp
- Thumbs.db
- Many.CESL
- Page58.cesl
- CEngineLog_06.26.04_13.17.20.txt
- CEngineLog_06.26.04_13.21.48.txt
- CEngineLog_06.26.04_13.21.59.txt
- CEngineLog_06.26.04_13.23.42.txt
- CEngineLog_06.26.04_13.23.51.txt
- CEngineLog_06.26.04_13.31.38.txt
- CEngineLog_06.28.04_12.15.12.txt
- CEngineLog_06.28.04_12.15.28.txt
- CEngineLog_06.30.04_15.39.22.txt
- try.cesl
- vc70.idb

(i)(CEngine): Creating source level (V&G)....
(i)(CircuitElement CE_NONAME.0): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.0): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Renaming...
(i)(CircuitElement Source(V&G).0): New name is OK.
(i)(Gate):(Type[Voltage],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[Ground],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(c)(CEngine): CE Empty:Source(V&G) is added into circuit.
(c)(CEngine): compilation started (D:\_Courses\_PASTU~1\DO6114~1\CMPE40~1\CEngine.net\Release\74LS08\74LS08~1.CES)....
Initializing BreadBoard Node Table(r20,c5)...
BreadBoard Node Table is ready.
Initializing BreadBoard Node Map Table(h6)...
BreadBoard Node Map Table is ready.
(i)(CircuitElement CE_NONAME.1): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.1): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Renaming...
(i)(CircuitElement 74LS08_AND_CHIP.1): New name is OK.
(c)(CEngine): CE CHIP:74LS08_AND_CHIP is now setting up by in-script information ....
(i)(CircuitElement 74LS08_AND_CHIP.1): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[14])::SetProps.() : properties OK.
(i)(CircuitElement 74LS08_AND_CHIP.1): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[7])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[5])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[9])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[10])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[13])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[6])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[8])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[11])::SetProps.() : properties OK.
(c)(CEngine): Gate List is OK for 74LS08_AND_CHIP.1..
(c)(CEngine): Gate connection process is starting for 74LS08_AND_CHIP.1....
(c)(CEngine): Gate connection process is completed..
(c)(CEngine): CE CHIP:74LS08_AND_CHIP is added into circuit.
(i)(CEngine): compilation completed....

LISTING CURRENT CIRCUIT ELEMENTS:

BREADBOARD : 20 rows, 5 cols and 6 holes in a node.

Gate List CE Source(V&G).id_0 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_0 (00000000), G = leg_0 (00000000)
Voltage(003C2580)(leg_0).1 >> 0 ()
Ground(003C25B8)(leg_0).2 >> 0 ()

Gate List CE 74LS08_AND_CHIP.id_1 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_14 (00000000), G = leg_7 (00000000)
Input(003C7D90)(leg_1).1 >> 1 ( 00000000 )
Input(003C7DC8)(leg_2).2 >> 1 ( 00000000 )
Input(003C7E00)(leg_4).3 >> 1 ( 00000000 )
Input(003C7E38)(leg_5).4 >> 1 ( 00000000 )
Input(003C7E70)(leg_9).5 >> 1 ( 00000000 )
Input(003C7EA8)(leg_10).6 >> 1 ( 00000000 )
Input(003C7EE0)(leg_12).7 >> 1 ( 00000000 )
Input(003C7F18)(leg_13).8 >> 1 ( 00000000 )
AND(003C7F50)(leg_3).9 >> 2 ( 003C7D90  003C7DC8 )
AND(003C7F88)(leg_6).10 >> 2 ( 003C7E00  003C7E38 )
AND(003C7FC0)(leg_8).11 >> 2 ( 003C7E70  003C7EA8 )
AND(003C7FF8)(leg_11).12 >> 2 ( 003C7EE0  003C7F18 )

END OF CIRCUIT LIST


(i)(CircuitElement CE_NONAME.2): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.2): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Renaming...
(i)(CircuitElement LED.2): New name is OK.
(i)(CircuitElement LED.2): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(CircuitElement LED.2): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(c)(CEngine): CE LED:LED is added into circuit.
(i)(CircuitElement CE_NONAME.3): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.3): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.3): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.3): Renaming...
(i)(CircuitElement CABLE.3): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.4): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.4): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.4): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.4): Renaming...
(i)(CircuitElement CABLE.4): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.5): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.5): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.5): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.5): Renaming...
(i)(CircuitElement LED.5): New name is OK.
(i)(CircuitElement LED.5): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(CircuitElement LED.5): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(c)(CEngine): CE LED:LED is added into circuit.
(i)(CircuitElement CE_NONAME.6): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.6): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.6): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.6): Renaming...
(i)(CircuitElement CABLE.6): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.7): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.7): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.7): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.7): Renaming...
(i)(CircuitElement CABLE.7): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.8): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.8): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.8): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.8): Renaming...
(i)(CircuitElement CABLE.8): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.

CABLE 003C82C8 (25,7)
Cable Node ID = 3

CABLE 003C83F8 (29,8)
Cable Node ID = 4

CABLE 003C8510 (28,1)
Cable Node ID = 4

CABLE 003C8658 (5,0)
Cable Node ID = 7

CABLE 003C8788 (21,0)
Cable Node ID = 7

CABLE 003C82C8 (25,7)
Cable Node ID = 3

CABLE 003C83F8 (29,8)
Cable Node ID = 4

CABLE 003C8510 (28,1)
Cable Node ID = 4

CABLE 003C8658 (5,0)
Cable Node ID = 7

CABLE 003C8788 (21,0)
Cable Node ID = 7
Deallocating BreadBoard Node Table...
Deallocating BreadBoard Node Map Table...
Deallocation of BreadBoard is completed.

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License

This article, along with any associated source code and files, is licensed under The GNU General Public License (GPLv3)

Written By

Emre Guldogan

Engineer Siemens

Turkey

I've graduated from computer engineering department in 2004 July, and developed the Circuit Engine as my graduation project at Eastern Mediterranean University (EMU). I've also graduated from MBA, Istanbul University in 2008 February. From 2004 until now, I've developed many web sites (B2B, B2C). Currently work for Siemens AG (http://siemens.com/ingenuityforlife) as a R&D Engineer (IoT) and I still continue to develop my personal projects about encryption algorithms, maths, OpenGL, Stock Exchange Market Analyses and Real-time Systems, MultiThreaded Applications and Web Solutions (mostly ASP.NET C#, JQuery/JS, MVC, WinForms, Win/Web Services, T-SQL and less PHP, ASP, MySQL and some possible other methods about problem solving if necessary). Also personal profession of photography : https://www.instagram.com/egldgn/

Circuit Engine base URL : https://sites.google.com/view/circuitengine

Circuit Engine

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