Circuit Engine

Emre Guldogan

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4.93/5 (103 votes)

18 Oct 2018GPL355 min read

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A System for Simulation and Analysis of Logic Circuits

circuitengine_-_executable.zip
- CEngine.exe
- Examples
  - 4BitAdder
    - 4bitAdder.cesl
  - 74LS08
    - 74LS08.cec
    - 74LS08.CESL
  - Asynchronous
    - Asynchronous.cec
    - Asynchronous.cesl
  - Dual4InputMux
    - 74153.pdf
    - DUAL4INPUTMUX.cec
    - DUAL4INPUTMUX.CESL
  - ExPage58
    - Page58.cesl
  - FullAdder
    - FullAdder.cec
    - FullAdder.CESL
  - FunctionF
    - FunctionF.cesl
- glut32.dll
- README BEFORE USE.txt
circuitengine_code_files_vs6.0.zip
- Artist.h
- BBNode.h
- Binary.h
- BreadBoard.h
- C.dep
- C.dsp
- C.dsw
- C.mak
- C.ncb
- C.opt
- C.plg
- C.sln
- C.suo
- C.vcproj
- ce.oldmain
- CEngine.cpp
- CEngine.h
- CircuitElement.h
- Debug
  - BuildLog.htm
  - C.pch
  - CEngine.exe
  - CEngine.ilk
  - CEngine.obj
  - CEngine.pdb
  - CEngine.sbr
  - CEngineLog_06.07.04_13.12.40.txt
  - CEngineLog_06.11.04_05.38.39.txt
  - try.cesl
  - vc70.idb
  - vc70.pdb
- Gate.h
- Release
  - 4BitAdder
    - 4bitAdder.cesl
    - CEngineLog_06.10.04_01.26.10.txt
    - CEngineLog_06.25.04_11.13.02.txt
    - CEngineLog_06.25.04_11.13.09.txt
    - CEngineLog_06.30.04_15.40.51.txt
  - 74LS08
    - 74LS08.CESL
    - CEngineLog_06.30.04_15.41.17.txt
  - Async1
    - Async1.cesl
    - ASYNC1~1.cec
    - CEngineLog_06.26.04_13.28.23.txt
    - CEngineLog_06.26.04_13.34.58.txt
    - CEngineLog_06.26.04_13.35.44.txt
    - CEngineLog_06.26.04_13.35.47.txt
    - CEngineLog_07.02.04_00.27.01.txt
  - BuildLog.htm
  - C.pch
  - C.pdb
  - CEngine.exe
  - CEngine.obj
  - DENEME.CESL
  - Dual4InputMux
    - 74153.pdf
    - CEngineLog_06.26.04_13.38.16.txt
    - CEngineLog_06.26.04_13.52.54.txt
    - DUAL4I~1.cec
    - DUAL4INPUTMUX.CESL
  - empty.cesl
  - ExPage58
    - Page58.cesl
  - FF.cesl
  - FullAdder
    - CEngineLog_06.26.04_13.59.41.txt
    - CEngineLog_06.27.04_15.07.48.txt
    - CEngineLog_06.28.04_12.17.08.txt
    - CEngineLog_06.28.04_12.18.36.txt
    - FULLAD~1.cec
    - fULLaDDER.CESL
  - FunctionF
    - CEngineLog_07.02.04_00.26.36.txt
    - FunctionF.cesl
    - InitialScreen.bmp
    - Thumbs.db
  - Many.CESL
  - Page58.cesl
  - SavedLogs
    - CEngineLog_06.26.04_13.17.20.txt
    - CEngineLog_06.26.04_13.21.48.txt
    - CEngineLog_06.26.04_13.21.59.txt
    - CEngineLog_06.26.04_13.23.42.txt
    - CEngineLog_06.26.04_13.23.51.txt
    - CEngineLog_06.26.04_13.31.38.txt
    - CEngineLog_06.28.04_12.15.12.txt
    - CEngineLog_06.28.04_12.15.28.txt
    - CEngineLog_06.30.04_15.39.22.txt
  - try.cesl
  - vc70.idb
cesl_cec_examples.zip
- 4bitAdder.cesl
- CEngineLog_06.10.04_01.26.10.txt
- 74LS08.CESL
- CEngineLog_06.30.04_15.41.17.txt
- Async1
  - Async1.cesl
  - ASYNC1~1.cec
  - CEngineLog_06.26.04_13.28.23.txt
  - 74153.pdf
  - CEngineLog_06.26.04_13.38.16.txt
  - DUAL4I~1.cec
  - DUAL4INPUTMUX.CESL
  - Page58.cesl
  - CEngineLog_06.26.04_13.59.41.txt
  - FULLAD~1.cec
  - fULLaDDER.CESL
  - CEngineLog_07.02.04_00.26.36.txt
  - FunctionF.cesl
glut-3.7.6-bin.zip
- glut-3.7.6-bin
  - glut.def
  - glut.h
  - glut32.dll
  - glut32.lib
  - README-win32.txt
circuitengine_code_files_vs6.0_vs8.0.zip
- Artist.h
- BBNode.h
- Binary.h
- BreadBoard.h
- C.vcproj
- CEngine.cpp
- CEngine.h
- Circuit Engine.sln
- CircuitElement.h
- 4bitAdder.cesl
- 74LS08.CESL
- Async1.cesl
- ASYNC1~1.cec
- Counter.cec
- Counter.cesl
- DUAL4I~1.cec
- DUAL4INPUTMUX.CESL
- FULLAD~1.cec
- fULLaDDER.CESL
- FunctionF.cesl
- Page58.cesl
- try.cesl
- Gate.h
glut-3.spec.zip
- glut-3.spec.pdf
circuitengine_code_files.zip
- Artist.h
- BBNode.h
- Binary.h
- BreadBoard.h
- C.dep
- C.dsp
- C.dsw
- C.mak
- C.ncb
- C.opt
- C.plg
- C.sln
- C.suo
- C.vcproj
- ce.oldmain
- CEngine.cpp
- CEngine.h
- CircuitElement.h
- BuildLog.htm
- C.pch
- CEngine.exe
- CEngine.ilk
- CEngine.obj
- CEngine.pdb
- CEngine.sbr
- CEngineLog_06.07.04_13.12.40.txt
- CEngineLog_06.11.04_05.38.39.txt
- try.cesl
- vc70.idb
- vc70.pdb
- Gate.h
- 4bitAdder.cesl
- CEngineLog_06.10.04_01.26.10.txt
- CEngineLog_06.25.04_11.13.02.txt
- CEngineLog_06.25.04_11.13.09.txt
- CEngineLog_06.30.04_15.40.51.txt
- 74LS08.CESL
- CEngineLog_06.30.04_15.41.17.txt
- Async1.cesl
- ASYNC1~1.cec
- CEngineLog_06.26.04_13.28.23.txt
- CEngineLog_06.26.04_13.34.58.txt
- CEngineLog_06.26.04_13.35.44.txt
- CEngineLog_06.26.04_13.35.47.txt
- CEngineLog_07.02.04_00.27.01.txt
- BuildLog.htm
- C.pch
- C.pdb
- CEngine.exe
- CEngine.obj
- DENEME.CESL
- 74153.pdf
- CEngineLog_06.26.04_13.38.16.txt
- CEngineLog_06.26.04_13.52.54.txt
- DUAL4I~1.cec
- DUAL4INPUTMUX.CESL
- empty.cesl
- Page58.cesl
- FF.cesl
- CEngineLog_06.26.04_13.59.41.txt
- CEngineLog_06.27.04_15.07.48.txt
- CEngineLog_06.28.04_12.17.08.txt
- CEngineLog_06.28.04_12.18.36.txt
- FULLAD~1.cec
- fULLaDDER.CESL
- CEngineLog_07.02.04_00.26.36.txt
- FunctionF.cesl
- InitialScreen.bmp
- Thumbs.db
- Many.CESL
- Page58.cesl
- CEngineLog_06.26.04_13.17.20.txt
- CEngineLog_06.26.04_13.21.48.txt
- CEngineLog_06.26.04_13.21.59.txt
- CEngineLog_06.26.04_13.23.42.txt
- CEngineLog_06.26.04_13.23.51.txt
- CEngineLog_06.26.04_13.31.38.txt
- CEngineLog_06.28.04_12.15.12.txt
- CEngineLog_06.28.04_12.15.28.txt
- CEngineLog_06.30.04_15.39.22.txt
- try.cesl
- vc70.idb

(i)(CEngine): Creating source level (V&G)....
(i)(CircuitElement CE_NONAME.0): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.0): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Renaming...
(i)(CircuitElement Source(V&G).0): New name is OK.
(i)(Gate):(Type[Voltage],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[Ground],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(c)(CEngine): CE Empty:Source(V&G) is added into circuit.
(c)(CEngine): compilation started (D:\_Courses\CMPE40~1\CEngine.net\Release\DUAL4I~1\DUAL4I~1.CES)....
Initializing BreadBoard Node Table(r30,c4)...
BreadBoard Node Table is ready.
Initializing BreadBoard Node Map Table(h6)...
BreadBoard Node Map Table is ready.
(i)(CircuitElement CE_NONAME.1): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.1): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Renaming...
(i)(CircuitElement Dual4InputMux.1): New name is OK.
(c)(CEngine): CE CHIP:Dual4InputMux is now setting up by in-script information ....
(i)(CircuitElement Dual4InputMux.1): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[16])::SetProps.() : properties OK.
(i)(CircuitElement Dual4InputMux.1): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[8])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[5])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[6])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[10])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[11])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[13])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[14])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[15])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[4],OutAsLeg[7])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[4],OutAsLeg[9])::SetProps.() : properties OK.
(c)(CEngine): Gate List is OK for Dual4InputMux.1..
(c)(CEngine): Gate connection process is starting for Dual4InputMux.1....
(c)(CEngine): Gate connection process is completed..
(c)(CEngine): CE CHIP:Dual4InputMux is added into circuit.
(i)(CEngine): compilation completed....

LISTING CURRENT CIRCUIT ELEMENTS:

BREADBOARD : 30 rows, 4 cols and 6 holes in a node.

Gate List CE Source(V&G).id_0 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_0 (00000000), G = leg_0 (00000000)
Voltage(003C2580)(leg_0).1 >> 0 ()
Ground(003C25B8)(leg_0).2 >> 0 ()

Gate List CE Dual4InputMux.id_1 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_16 (00000000), G = leg_8 (00000000)
Input(003C8180)(leg_1).1 >> 1 ( 00000000 )
Input(003C81B8)(leg_2).2 >> 1 ( 00000000 )
Input(003C81F0)(leg_3).3 >> 1 ( 00000000 )
Input(003C8228)(leg_4).4 >> 1 ( 00000000 )
Input(003C8260)(leg_5).5 >> 1 ( 00000000 )
Input(003C8298)(leg_6).6 >> 1 ( 00000000 )
Input(003C82D0)(leg_10).7 >> 1 ( 00000000 )
Input(003C8308)(leg_11).8 >> 1 ( 00000000 )
Input(003C8340)(leg_12).9 >> 1 ( 00000000 )
Input(003C8378)(leg_13).10 >> 1 ( 00000000 )
Input(003C83B0)(leg_14).11 >> 1 ( 00000000 )
Input(003C83E8)(leg_15).12 >> 1 ( 00000000 )
NOT(003C8420)(leg_0).13 >> 1 ( 003C8180 )
NOT(003C8458)(leg_0).14 >> 1 ( 003C81B8 )
NOT(003C8490)(leg_0).15 >> 1 ( 003C83B0 )
NOT(003C84C8)(leg_0).16 >> 1 ( 003C83E8 )
NOT(003C8500)(leg_0).17 >> 1 ( 003C81B8 )
NOT(003C8538)(leg_0).18 >> 1 ( 003C81F0 )
AND(003C8570)(leg_0).19 >> 4 ( 003C8180  003C81B8  003C81F0  003C8298 )
AND(003C85B0)(leg_0).20 >> 4 ( 003C8180  003C81B8  003C8298  003C8260 )
AND(003C85F0)(leg_0).21 >> 4 ( 003C8180  003C8260  003C81F0  003C8228 )
AND(003C8630)(leg_0).22 >> 4 ( 003C8180  003C8260  003C8298  003C81F0 )
AND(003C8670)(leg_0).23 >> 4 ( 003C82D0  003C81B8  003C81F0  003C8228 )
AND(003C86B0)(leg_0).24 >> 4 ( 003C8308  003C81B8  003C8298  003C8228 )
AND(003C86F0)(leg_0).25 >> 4 ( 003C8340  003C8260  003C81F0  003C8228 )
AND(003C8730)(leg_0).26 >> 4 ( 003C8378  003C8260  003C8298  003C8228 )
OR(003C8770)(leg_7).27 >> 4 ( 003C8180  003C81B8  003C81F0  003C8228 )
OR(003C87B0)(leg_9).28 >> 4 ( 003C8260  003C8298  003C82D0  003C8308 )

END OF CIRCUIT LIST


(i)(CircuitElement CE_NONAME.2): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.2): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Renaming...
(i)(CircuitElement CABLE.2): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.3): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.3): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.3): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.3): Renaming...
(i)(CircuitElement CABLE.3): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.4): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.4): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.4): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.4): Renaming...
(i)(CircuitElement CABLE.4): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.5): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.5): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.5): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.5): Renaming...
(i)(CircuitElement CABLE.5): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.6): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.6): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.6): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.6): Renaming...
(i)(CircuitElement CABLE.6): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.7): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.7): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.7): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.7): Renaming...
(i)(CircuitElement CABLE.7): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.8): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.8): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.8): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.8): Renaming...
(i)(CircuitElement CABLE.8): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.9): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.9): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.9): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.9): Renaming...
(i)(CircuitElement CABLE.9): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.10): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.10): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.10): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.10): Renaming...
(i)(CircuitElement LED.10): New name is OK.
(i)(CircuitElement LED.10): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(CircuitElement LED.10): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(c)(CEngine): CE LED:LED is added into circuit.
(i)(CircuitElement CE_NONAME.11): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.11): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.11): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.11): Renaming...
(i)(CircuitElement CABLE.11): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.12): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.12): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.12): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.12): Renaming...
(i)(CircuitElement CABLE.12): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.13): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.13): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.13): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.13): Renaming...
(i)(CircuitElement CABLE.13): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.14): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.14): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.14): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.14): Renaming...
(i)(CircuitElement CABLE.14): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.15): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.15): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.15): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.15): Renaming...
(i)(CircuitElement CABLE.15): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.16): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.16): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.16): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.16): Renaming...
(i)(CircuitElement CABLE.16): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.17): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.17): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.17): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.17): Renaming...
(i)(CircuitElement CABLE.17): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.18): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.18): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.18): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.18): Renaming...
(i)(CircuitElement CABLE.18): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
Deallocating BreadBoard Node Table...
Deallocating BreadBoard Node Map Table...
Deallocation of BreadBoard is completed.

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License

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Written By

Emre Guldogan

Engineer Siemens

Turkey

I've graduated from computer engineering department in 2004 July, and developed the Circuit Engine as my graduation project at Eastern Mediterranean University (EMU). I've also graduated from MBA, Istanbul University in 2008 February. From 2004 until now, I've developed many web sites (B2B, B2C). Currently work for Siemens AG (http://siemens.com/ingenuityforlife) as a R&D Engineer (IoT) and I still continue to develop my personal projects about encryption algorithms, maths, OpenGL, Stock Exchange Market Analyses and Real-time Systems, MultiThreaded Applications and Web Solutions (mostly ASP.NET C#, JQuery/JS, MVC, WinForms, Win/Web Services, T-SQL and less PHP, ASP, MySQL and some possible other methods about problem solving if necessary). Also personal profession of photography : https://www.instagram.com/egldgn/

Circuit Engine base URL : https://sites.google.com/view/circuitengine

Circuit Engine

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