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#if !defined(_PICPC_H_)
#define _PICPC_H_
#include "typedefs.h"
/*
* Header file for the Microchip
* PIC 16F870
* PIC 16F871
* PIC 16F872 chip
* PIC 16F873 chip
* PIC 16F874 chip
* PIC 16F876 chip
* PIC 16F877 chip
* PIC 16F873A chip
* PIC 16F874A chip
* PIC 16F876A chip
* PIC 16F877A chip
* Midrange Microcontroller
*/
typedef unsigned char bit;
// EEPROM-Internal
extern UBYTE _EEPROMRead( UBYTE addr );
extern void EEPROMRead( UBYTE addr, UBYTE size, UBYTE* data );
extern void _EEPROMWrite( UBYTE addr, UBYTE data );
extern void EEPROMWrite( UBYTE addr, UBYTE size, UBYTE* data );
// adc
extern void adc_init_channels( void );
extern UBYTE adc_continue( void );
extern UINT16 adc_get_adres( void );
extern UINT16 adc_read( UBYTE adc_ch );
extern void adc_start( UBYTE adc_ch );
extern ADC_SETUP0(UBYTE _adc0);
extern ADC_SETUP1(UBYTE _adc1);
// timer 0
extern TIMER0_EVENT_ENABLE();
extern TIMER0_EVENT_DISABLE();
extern TIMER0_SET( UBYTE _tmr0 );
// timer 1
extern TIMER1_EVENT_ENABLE();
extern TIMER1_EVENT_DISABLE();
extern TIMER1_SET( UINT16 _tmr1 );
extern TIMER1_SETUP( UBYTE _t1con );
// timer 2
extern TIMER2_SETUP( UBYTE _t2con );
// cpp
extern PWM_FREQ_SETUP( UBYTE freq );
extern PWM1_DC_SETUP( UINT16 dc );
extern CCP1_SETUP( UBYTE _ccp1 );
extern CCP2_SETUP( UBYTE _ccp2 );
extern PWM2_DC_SETUP( UINT16 dc );
extern CLRWDT();
extern SET_OPTION( UBYTE _option );
extern void isr( void );
extern volatile UINT16 timer1_clone;
extern volatile UINT16 ccpr1_clone;
extern volatile UINT16 ccpr2_clone;
#define _16F870
#define interrupt
#define bank1
#define bank2
#define bank3
#define asm(x)
#define __CONFIG(x)
#if defined(_16F874) || defined(_16F877) || defined(_16F871) || \
defined(_16F874A) || defined(_16F877A)
#define __PINS_40
#endif
#if defined(_16F873A) || defined(_16F874A) || defined(_16F876A) || \
defined(_16F877A)
#define __A_TYPE
#endif
extern volatile unsigned char INDF; // 0x00;
extern volatile unsigned char TMR0; // 0x01;
extern volatile unsigned char PCL; // 0x02;
extern volatile unsigned char STATUS; // 0x03;
extern unsigned char FSR; // 0x04;
extern volatile unsigned char PORTA; // 0x05;
extern volatile unsigned char PORTB; // 0x06;
extern volatile unsigned char PORTC; // 0x07;
#ifdef __PINS_40
extern volatile unsigned char PORTD; // 0x08;
extern volatile unsigned char PORTE; // 0x09;
#endif
extern unsigned char PCLATH; // 0x0A;
extern volatile unsigned char INTCON; // 0x0B;
extern volatile unsigned char PIR1; // 0x0C;
extern volatile unsigned char PIR2; // 0x0D;
extern volatile unsigned char TMR1L; // 0x0E;
extern volatile unsigned char TMR1H; // 0x0F;
extern volatile unsigned char T1CON; // 0x10;
extern volatile unsigned char TMR2; // 0x11;
extern volatile unsigned char T2CON; // 0x12;
#if !defined(_16F870) && !defined(_16F871)
extern volatile unsigned char SSPBUF; // 0x13;
extern volatile unsigned char SSPCON; // 0x14;
#endif
extern volatile unsigned char CCPR1L; // 0x15;
extern volatile unsigned char CCPR1H; // 0x16;
extern volatile unsigned char CCP1CON; // 0x17;
#ifndef _16F872
extern volatile unsigned char RCSTA; // 0x18;
extern volatile unsigned char TXREG; // 0x19;
extern volatile unsigned char RCREG; // 0x1A;
#if !defined(_16F870) && !defined(_16F871)
extern volatile unsigned char CCPR2L; // 0x1B;
extern volatile unsigned char CCPR2H; // 0x1C;
extern volatile unsigned char CCP2CON; // 0x1D;
#endif
#endif
extern volatile unsigned char ADRESH; // 0x1E;
extern volatile unsigned char ADCON0; // 0x1F;
/* bank 1 registers */
extern unsigned char bank1 OPTION; // 0x81;
extern volatile unsigned char bank1 TRISA; // 0x85;
extern volatile unsigned char bank1 TRISB; // 0x86;
extern volatile unsigned char bank1 TRISC; // 0x87;
#ifdef __PINS_40
extern volatile unsigned char bank1 TRISD; // 0x88;
extern volatile unsigned char bank1 TRISE; // 0x89;
#endif
extern volatile unsigned char bank1 PIE1; // 0x8C;
extern volatile unsigned char bank1 PIE2; // 0x8D;
extern volatile unsigned char bank1 PCON; // 0x8E;
#if !defined(_16F870) && !defined(_16F871)
extern volatile unsigned char bank1 SSPCON2; // 0x91;
#endif
extern volatile unsigned char bank1 PR2; // 0x92;
#if !defined(_16F870) && !defined(_16F871)
extern volatile unsigned char bank1 SSPADD; // 0x93;
extern volatile unsigned char bank1 SSPSTAT; // 0x94;
#endif
#ifndef _16F872
extern volatile unsigned char bank1 TXSTA; // 0x98;
extern volatile unsigned char bank1 SPBRG; // 0x99;
#endif
#ifdef __A_TYPE
extern volatile unsigned char bank1 CMCON; // 0x9C;
extern volatile unsigned char bank1 CVRCON; // 0x9D;
#endif
extern volatile unsigned char bank1 ADRESL; // 0x9E;
extern volatile unsigned char bank1 ADCON1; // 0x9F;
/* bank 2 registers */
extern volatile unsigned char bank2 EEDATA; // 0x10C;
extern volatile unsigned char bank2 EEADR; // 0x10D;
extern volatile unsigned char bank2 EEDATH; // 0x10E;
extern volatile unsigned char bank2 EEADRH; // 0x10F;
/* bank 3 registers */
extern volatile unsigned char bank3 EECON1; // 0x18C;
extern volatile unsigned char bank3 EECON2; // 0x18D;
/* STATUS bits */
extern volatile bit IRP ; // (unsigned)&STATUS*8+7;
extern volatile bit RP1 ; // (unsigned)&STATUS*8+6;
extern volatile bit RP0 ; // (unsigned)&STATUS*8+5;
extern volatile bit TO; // (unsigned)&STATUS*8+4;
extern volatile bit PD; // (unsigned)&STATUS*8+3;
extern volatile bit ZERO ; // (unsigned)&STATUS*8+2;
extern volatile bit DC ; // (unsigned)&STATUS*8+1;
extern volatile bit CARRY ; // (unsigned)&STATUS*8+0;
/* PORTA bits */
extern volatile bit RA5; // (unsigned)&PORTA*8+5;
extern volatile bit RA4; // (unsigned)&PORTA*8+4;
extern volatile bit RA3; // (unsigned)&PORTA*8+3;
extern volatile bit RA2; // (unsigned)&PORTA*8+2;
extern volatile bit RA1; // (unsigned)&PORTA*8+1;
extern volatile bit RA0; // (unsigned)&PORTA*8+0;
/* PORTB bits */
extern volatile bit RB7; // (unsigned)&PORTB*8+7;
extern volatile bit RB6; // (unsigned)&PORTB*8+6;
extern volatile bit RB5; // (unsigned)&PORTB*8+5;
extern volatile bit RB4; // (unsigned)&PORTB*8+4;
extern volatile bit RB3; // (unsigned)&PORTB*8+3;
extern volatile bit RB2; // (unsigned)&PORTB*8+2;
extern volatile bit RB1; // (unsigned)&PORTB*8+1;
extern volatile bit RB0; // (unsigned)&PORTB*8+0;
/* PORTC bits */
extern volatile bit RC7; // (unsigned)&PORTC*8+7;
extern volatile bit RC6; // (unsigned)&PORTC*8+6;
extern volatile bit RC5; // (unsigned)&PORTC*8+5;
extern volatile bit RC4; // (unsigned)&PORTC*8+4;
extern volatile bit RC3; // (unsigned)&PORTC*8+3;
extern volatile bit RC2; // (unsigned)&PORTC*8+2;
extern volatile bit RC1; // (unsigned)&PORTC*8+1;
extern volatile bit RC0; // (unsigned)&PORTC*8+0;
/* PORTD bits */
#ifdef __PINS_40
extern volatile bit RD7; // (unsigned)&PORTD*8+7;
extern volatile bit RD6; // (unsigned)&PORTD*8+6;
extern volatile bit RD5; // (unsigned)&PORTD*8+5;
extern volatile bit RD4; // (unsigned)&PORTD*8+4;
extern volatile bit RD3; // (unsigned)&PORTD*8+3;
extern volatile bit RD2; // (unsigned)&PORTD*8+2;
extern volatile bit RD1; // (unsigned)&PORTD*8+1;
extern volatile bit RD0; // (unsigned)&PORTD*8+0;
/* PORTE bits */
extern volatile bit RE2; // (unsigned)&PORTE*8+2;
extern volatile bit RE1; // (unsigned)&PORTE*8+1;
extern volatile bit RE0; // (unsigned)&PORTE*8+0;
#endif
/* INTCON bits */
extern volatile bit GIE; // (unsigned)&INTCON*8+7;
extern volatile bit PEIE; // (unsigned)&INTCON*8+6;
extern volatile unsigned char T0IE; // (unsigned)&INTCON*8+5;
extern volatile bit INTE; // (unsigned)&INTCON*8+4;
extern volatile bit RBIE; // (unsigned)&INTCON*8+3;
extern volatile bit T0IF; // (unsigned)&INTCON*8+2;
extern volatile bit INTF; // (unsigned)&INTCON*8+1;
extern volatile bit RBIF; // (unsigned)&INTCON*8+0;
// alternate definitions
extern volatile bit TMR0IE; // (unsigned)&INTCON*8+5;
extern volatile bit TMR0IF; // (unsigned)&INTCON*8+2;
/* PIR1 bits */
#ifdef __PINS_40
extern volatile bit PSPIF; // (unsigned)&PIR1*8+7;
#endif
extern volatile bit ADIF; // (unsigned)&PIR1*8+6;
#ifndef _16F872
extern volatile bit RCIF; // (unsigned)&PIR1*8+5;
extern volatile bit TXIF; // (unsigned)&PIR1*8+4;
#endif
#if !defined(_16F870) && !defined(_16F871)
extern volatile bit SSPIF; // (unsigned)&PIR1*8+3;
#endif
extern volatile bit CCP1IF; // (unsigned)&PIR1*8+2;
extern volatile bit TMR2IF; // (unsigned)&PIR1*8+1;
extern volatile bit TMR1IF; // (unsigned)&PIR1*8+0;
/* PIR2 bits */
#ifdef __A_TYPE
extern volatile bit CMIF; // (unsigned)&PIR2*8+6;
#endif
extern volatile bit EEIF; // (unsigned)&PIR2*8+4;
#if !defined(_16F870) && !defined(_16F871)
extern volatile bit BCLIF; // (unsigned)&PIR2*8+3;
#ifndef _16F872
extern volatile bit CCP2IF; // (unsigned)&PIR2*8+0;
#endif
#endif
/* T1CON bits */
extern volatile bit T1CKPS1; // (unsigned)&T1CON*8+5;
extern volatile bit T1CKPS0; // (unsigned)&T1CON*8+4;
extern volatile bit T1OSCEN; // (unsigned)&T1CON*8+3;
extern volatile bit T1SYNC ; // (unsigned)&T1CON*8+2;
extern volatile bit TMR1CS ; // (unsigned)&T1CON*8+1;
extern volatile bit TMR1ON ; // (unsigned)&T1CON*8+0;
/* T2CON bits */
extern volatile bit TOUTPS3; // (unsigned)&T2CON*8+6;
extern volatile bit TOUTPS2; // (unsigned)&T2CON*8+5;
extern volatile bit TOUTPS1; // (unsigned)&T2CON*8+4;
extern volatile bit TOUTPS0; // (unsigned)&T2CON*8+3;
extern volatile bit TMR2ON ; // (unsigned)&T2CON*8+2;
extern volatile bit T2CKPS1; // (unsigned)&T2CON*8+1;
extern volatile bit T2CKPS0; // (unsigned)&T2CON*8+0;
/* SSPCON bits */
#if !defined(_16F870) && !defined(_16F871)
extern volatile bit WCOL; // (unsigned)&SSPCON*8+7;
extern volatile bit SSPOV; // (unsigned)&SSPCON*8+6;
extern volatile bit SSPEN; // (unsigned)&SSPCON*8+5;
extern volatile bit CKP; // (unsigned)&SSPCON*8+4;
extern volatile bit SSPM3; // (unsigned)&SSPCON*8+3;
extern volatile bit SSPM2; // (unsigned)&SSPCON*8+2;
extern volatile bit SSPM1; // (unsigned)&SSPCON*8+1;
extern volatile bit SSPM0; // (unsigned)&SSPCON*8+0;
#endif
/* CCP1CON bits */
extern volatile bit CCP1X; // (unsigned)&CCP1CON*8+5;
extern volatile bit CCP1Y; // (unsigned)&CCP1CON*8+4;
extern volatile bit CCP1M3; // (unsigned)&CCP1CON*8+3;
extern volatile bit CCP1M2; // (unsigned)&CCP1CON*8+2;
extern volatile bit CCP1M1; // (unsigned)&CCP1CON*8+1;
extern volatile bit CCP1M0; // (unsigned)&CCP1CON*8+0;
/* RCSTA bits */
#ifndef _16F872
extern volatile bit SPEN; // (unsigned)&RCSTA*8+7;
extern volatile bit RX9 ; // (unsigned)&RCSTA*8+6;
extern volatile bit SREN; // (unsigned)&RCSTA*8+5;
extern volatile bit CREN; // (unsigned)&RCSTA*8+4;
extern volatile bit ADDEN; // (unsigned)&RCSTA*8+3;
extern volatile bit FERR; // (unsigned)&RCSTA*8+2;
extern volatile bit OERR; // (unsigned)&RCSTA*8+1;
extern volatile bit RX9D; // (unsigned)&RCSTA*8+0;
#endif
/* CCP2CON bits */
#if !defined(_16F870) && !defined(_16F871) && !defined(_16F872)
extern volatile bit CCP2X; // (unsigned)&CCP2CON*8+5;
extern volatile bit CCP2Y; // (unsigned)&CCP2CON*8+4;
extern volatile bit CCP2M3; // (unsigned)&CCP2CON*8+3;
extern volatile bit CCP2M2; // (unsigned)&CCP2CON*8+2;
extern volatile bit CCP2M1; // (unsigned)&CCP2CON*8+1;
extern volatile bit CCP2M0; // (unsigned)&CCP2CON*8+0;
#endif
/* ADCON0 bits */
extern volatile bit ADCS1; // (unsigned)&ADCON0*8+7;
extern volatile bit ADCS0 ; // (unsigned)&ADCON0*8+6;
extern volatile bit CHS2; // (unsigned)&ADCON0*8+5;
extern volatile bit CHS1; // (unsigned)&ADCON0*8+4;
extern volatile bit CHS0; // (unsigned)&ADCON0*8+3;
extern volatile bit ADGO; // (unsigned)&ADCON0*8+2;
extern volatile bit ADON; // (unsigned)&ADCON0*8+0;
/* OPTION bits */
extern bank1 bit RBPU; // (unsigned)&OPTION*8+7;
extern bank1 bit INTEDG; // (unsigned)&OPTION*8+6;
extern bank1 bit T0CS; // (unsigned)&OPTION*8+5;
extern bank1 bit T0SE; // (unsigned)&OPTION*8+4;
extern bank1 bit PSA; // (unsigned)&OPTION*8+3;
extern bank1 bit PS2; // (unsigned)&OPTION*8+2;
extern bank1 bit PS1; // (unsigned)&OPTION*8+1;
extern bank1 bit PS0; // (unsigned)&OPTION*8+0;
/* TRISA bits */
extern volatile bank1 bit TRISA5; // (unsigned)&TRISA*8+5;
extern volatile bank1 bit TRISA4; // (unsigned)&TRISA*8+4;
extern volatile bank1 bit TRISA3; // (unsigned)&TRISA*8+3;
extern volatile bank1 bit TRISA2; // (unsigned)&TRISA*8+2;
extern volatile bank1 bit TRISA1; // (unsigned)&TRISA*8+1;
extern volatile bank1 bit TRISA0; // (unsigned)&TRISA*8+0;
/* TRISB bits */
extern volatile bank1 bit TRISB7; // (unsigned)&TRISB*8+7;
extern volatile bank1 bit TRISB6; // (unsigned)&TRISB*8+6;
extern volatile bank1 bit TRISB5; // (unsigned)&TRISB*8+5;
extern volatile bank1 bit TRISB4; // (unsigned)&TRISB*8+4;
extern volatile bank1 bit TRISB3; // (unsigned)&TRISB*8+3;
extern volatile bank1 bit TRISB2; // (unsigned)&TRISB*8+2;
extern volatile bank1 bit TRISB1; // (unsigned)&TRISB*8+1;
extern volatile bank1 bit TRISB0; // (unsigned)&TRISB*8+0;
/* TRISC bits */
extern volatile bank1 bit TRISC7; // (unsigned)&TRISC*8+7;
extern volatile bank1 bit TRISC6; // (unsigned)&TRISC*8+6;
extern volatile bank1 bit TRISC5; // (unsigned)&TRISC*8+5;
extern volatile bank1 bit TRISC4; // (unsigned)&TRISC*8+4;
extern volatile bank1 bit TRISC3; // (unsigned)&TRISC*8+3;
extern volatile bank1 bit TRISC2; // (unsigned)&TRISC*8+2;
extern volatile bank1 bit TRISC1; // (unsigned)&TRISC*8+1;
extern volatile bank1 bit TRISC0; // (unsigned)&TRISC*8+0;
#ifdef __PINS_40
/* TRISD bits */
extern volatile bank1 bit TRISD7; // (unsigned)&TRISD*8+7;
extern volatile bank1 bit TRISD6; // (unsigned)&TRISD*8+6;
extern volatile bank1 bit TRISD5; // (unsigned)&TRISD*8+5;
extern volatile bank1 bit TRISD4; // (unsigned)&TRISD*8+4;
extern volatile bank1 bit TRISD3; // (unsigned)&TRISD*8+3;
extern volatile bank1 bit TRISD2; // (unsigned)&TRISD*8+2;
extern volatile bank1 bit TRISD1; // (unsigned)&TRISD*8+1;
extern volatile bank1 bit TRISD0; // (unsigned)&TRISD*8+0;
/* TRISE bits */
extern volatile bank1 bit IBF; // (unsigned)&TRISE*8+7;
extern volatile bank1 bit OBF; // (unsigned)&TRISE*8+6;
extern volatile bank1 bit IBOV; // (unsigned)&TRISE*8+5;
extern volatile bank1 bit PSPMODE; // (unsigned)&TRISE*8+4;
extern volatile bank1 bit TRISE2 ; // (unsigned)&TRISE*8+2;
extern volatile bank1 bit TRISE1 ; // (unsigned)&TRISE*8+1;
extern volatile bank1 bit TRISE0 ; // (unsigned)&TRISE*8+0;
#endif
/* PIE1 bits */
#ifdef __PINS_40
extern volatile bank1 bit PSPIE; // (unsigned)&PIE1*8+7;
#endif
extern volatile bank1 bit ADIE; // (unsigned)&PIE1*8+6;
#ifndef _16F872
extern volatile bank1 bit RCIE; // (unsigned)&PIE1*8+5;
extern volatile bank1 bit TXIE; // (unsigned)&PIE1*8+4;
#endif
extern volatile bank1 bit SSPIE; // (unsigned)&PIE1*8+3;
extern volatile bank1 bit CCP1IE; // (unsigned)&PIE1*8+2;
extern volatile bank1 bit TMR2IE; // (unsigned)&PIE1*8+1;
extern volatile bank1 bit TMR1IE; // (unsigned)&PIE1*8+0;
/* PIE2 bits */
#ifdef __A_TYPE
extern volatile bank1 bit CMIE; // (unsigned)&PIE2*8+6;
#endif
extern volatile bank1 bit EEIE; // (unsigned)&PIE2*8+4;
extern volatile bank1 bit BCLIE; // (unsigned)&PIE2*8+3;
#ifndef _16F872
extern volatile bank1 bit CCP2IE; // (unsigned)&PIE2*8+0;
#endif
/* PCON bits */
extern volatile bank1 bit POR; // (unsigned)&PCON*8+1;
extern volatile bank1 bit BOR; // (unsigned)&PCON*8+0;
/* SSPCON2 bits */
#if !defined(_16F870) && !defined(_16F871)
extern volatile bank1 bit GCEN; // (unsigned)&SSPCON2*8+7;
extern volatile bank1 bit ACKSTAT; // (unsigned)&SSPCON2*8+6;
extern volatile bank1 bit ACKDT; // (unsigned)&SSPCON2*8+5;
extern volatile bank1 bit ACKEN; // (unsigned)&SSPCON2*8+4;
extern volatile bank1 bit RCEN; // (unsigned)&SSPCON2*8+3;
extern volatile bank1 bit PEN; // (unsigned)&SSPCON2*8+2;
extern volatile bank1 bit RSEN; // (unsigned)&SSPCON2*8+1;
extern volatile bank1 bit SEN; // (unsigned)&SSPCON2*8+0;
#endif
/* SSPSTAT bits */
#if !defined(_16F870) && !defined(_16F871)
extern volatile bank1 bit STAT_SMP; // (unsigned)&SSPSTAT*8+7;
extern volatile bank1 bit STAT_CKE; // (unsigned)&SSPSTAT*8+6;
extern volatile bank1 bit STAT_DA ; // (unsigned)&SSPSTAT*8+5;
extern volatile bank1 bit STAT_P ; // (unsigned)&SSPSTAT*8+4;
extern volatile bank1 bit STAT_S ; // (unsigned)&SSPSTAT*8+3;
extern volatile bank1 bit STAT_RW ; // (unsigned)&SSPSTAT*8+2;
extern volatile bank1 bit STAT_UA ; // (unsigned)&SSPSTAT*8+1;
extern volatile bank1 bit STAT_BF ; // (unsigned)&SSPSTAT*8+0;
#endif
/* TXSTA bits */
#ifndef _16F872
extern volatile bank1 bit CSRC; // (unsigned)&TXSTA*8+7;
extern volatile bank1 bit TX9; // (unsigned)&TXSTA*8+6;
extern volatile bank1 bit TXEN; // (unsigned)&TXSTA*8+5;
extern volatile bank1 bit SYNC; // (unsigned)&TXSTA*8+4;
extern volatile bank1 bit BRGH; // (unsigned)&TXSTA*8+2;
extern volatile bank1 bit TRMT; // (unsigned)&TXSTA*8+1;
extern volatile bank1 bit TX9D; // (unsigned)&TXSTA*8+0;
#endif
#ifdef __A_TYPE
/* CMCON Bits */
extern volatile bank1 bit C2OUT; // (unsigned)&CMCON*8+7;
extern volatile bank1 bit C1OUT; // (unsigned)&CMCON*8+6;
extern volatile bank1 bit C2INV; // (unsigned)&CMCON*8+5;
extern volatile bank1 bit C1INV; // (unsigned)&CMCON*8+4;
extern volatile bank1 bit CIS; // (unsigned)&CMCON*8+3;
extern volatile bank1 bit CM2; // (unsigned)&CMCON*8+2;
extern volatile bank1 bit CM1; // (unsigned)&CMCON*8+1;
extern volatile bank1 bit CM0; // (unsigned)&CMCON*8+0;
/* CVRCON Bits */
extern volatile bank1 bit CVREN; // (unsigned)&CVRCON*8+7;
extern volatile bank1 bit CVROE; // (unsigned)&CVRCON*8+6;
extern volatile bank1 bit CVRR; // (unsigned)&CVRCON*8+5;
extern volatile bank1 bit CVR3; // (unsigned)&CVRCON*8+3;
extern volatile bank1 bit CVR2; // (unsigned)&CVRCON*8+2;
extern volatile bank1 bit CVR1; // (unsigned)&CVRCON*8+1;
extern volatile bank1 bit CVR0; // (unsigned)&CVRCON*8+0;
#endif
/* ADCON1 bits */
extern volatile bank1 bit ADFM; // (unsigned)&ADCON1*8+7;
#ifdef __A_TYPE
extern volatile bank1 bit ADCS2; // (unsigned)&ADCON1*8+6;
#endif
extern volatile bank1 bit PCFG3; // (unsigned)&ADCON1*8+3;
extern volatile bank1 bit PCFG2; // (unsigned)&ADCON1*8+2;
extern volatile bank1 bit PCFG1; // (unsigned)&ADCON1*8+1;
extern volatile bank1 bit PCFG0; // (unsigned)&ADCON1*8+0;
/* EECON1 bits */
extern volatile bank3 bit EEPGD; // (unsigned)&EECON1*8+7;
extern volatile bank3 bit WRERR; // (unsigned)&EECON1*8+3;
extern volatile bank3 bit WREN; // (unsigned)&EECON1*8+2;
extern volatile bank3 bit WR; // (unsigned)&EECON1*8+1;
extern volatile bank3 bit RD; // (unsigned)&EECON1*8+0;
#if defined(_16F870) || defined(_16F871) || defined(_16F872)
#define EEPROM_SIZE 64
#elif defined(_16F873) || defined(_16F873A) ||\
defined(_16F874) || defined(_16F874A)
#define EEPROM_SIZE 128
#else
#define EEPROM_SIZE 256
#endif
/* macro versions of EEPROM write and read */
#define EEPROM_WRITE(addr, value) while(WR)continue;EEADR=(addr);EEDATA=(value); \
EEPGD=0;CARRY=0;if(GIE)CARRY=1;GIE=0; \
WREN=1;EECON2=0x55;EECON2=0xAA;WR=1;WREN=0; \
if(CARRY)GIE=1
#define EEPROM_READ(addr) ((EEADR=(addr)),(EEPGD=0),(RD=1),EEDATA)
/* macro versions of Flash read and write */
#define FLASH_WRITE(addr, value) EEADR=((addr)&0xff); \
EEADRH=((addr)>>8); \
EEDATH=((value)>>8); \
EEDATA=((value)&0xff); \
EEPGD = 1; \
WREN=1; \
EECON2 = 0x55; \
EECON2 = 0xaa; \
WR=1; \
asm("nop"); \
asm("nop"); \
WREN=0
#define FLASH_READ(addr) EEADR=((addr)&0xff); \
EEADRH=((addr)>>8); \
WREN=0; \
EEPGD = 1; \
RD=1; \
asm("nop"); \
asm("nop"); \
((EEDATH << 8) | EEDATA)
/* library function versions */
extern void eeprom_write(unsigned char addr, unsigned char value);
extern unsigned char eeprom_read(unsigned char addr);
#define CONFIG_ADDR 0x2007
/*osc configurations*/
#define RC 0x3FFF // resistor/capacitor
#define HS 0x3FFE // high speed crystal/resonator
#define XT 0x3FFD // crystal/resonator
#define LP 0x3FFC // low power crystal/resonator
/*watchdog*/
#define WDTEN 0x3FFF // enable watchdog timer
#define WDTDIS 0x3FFB // disable watchdog timer
/*power up timer*/
#define PWRTEN 0x3FF7 // enable power up timer
#define PWRTDIS 0x3FFF // disable power up timer
/*brown out reset*/
#define BOREN 0x3FFF // enable brown out reset
#define BORDIS 0x3FBF // disable brown out reset
/*Low Voltage Programmable*/
#define LVPEN 0x3FFF // low voltage programming enabled
#define LVPDIS 0x3F7F // low voltage programming disabled
/*data code protected*/
#define DP 0x3EFF // protect data code
// alternately
#define DPROT 0x3EFF // use DP
#define DUNPROT 0x3FFF // use UNPROTECT
/* Flash memory write enable/protect */
#define WRTEN 0x3FFF /* flash memory write enabled */
#if defined(__A_TYPE)
#define WP1 0x3DFF /* protect 0000 - 00FF */
#define WP2 0x3BFF /* protect 0000 - 07FF(76A/77A) / 03FF(73A/74A) */
#define WP3 0x39FF /* protect 0000 - 1FFF(76A/77A) / 0FFF(73A/74A) */
#else
#define WRTDIS 0x3DFF /* flash memory write protected/disabled */
#endif
/*debug option*/
#define DEBUGEN 0x37FF // debugger enabled
#define DEBUGDIS 0x3FFF // debugger disabled
/*code protection*/
#ifdef __A_TYPE
#define PROTECT 0x1FFF /* protect program code */
#else
#define PROTECT 0x0FCF /* protect program code */
#endif
#define UNPROTECT 0x3FFF /* do not protect the code */
#if !defined(_16F870) && !defined(_16F871) && !defined(__A_TYPE)
#define PROTECT_TOP 0x2FEF /* protects top 256 bytes, 1F00h to 1FFFh */
#define PROTECT50 0x1FDF /* protects upper half of address space */
/* 1000h to 1FFFh (pic16f887/876) */
/* 0800h to 0FFFh (pic16f874/873) */
#endif
#endif // _PICPC_H_
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