Xilinx FPGA with AVRILOS

grilialex

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9 Nov 2011CDDL21 min read

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How-To Embed Xilinx FPGA Configuration Data to AVRILOS

avr16_V120.zip
- avr16
  - build.dep
    - adc.P
    - applic.P
    - dbgext.P
    - debugger.P
    - delay.P
    - eeprom.P
    - fpga_cfg.P
    - fpgassi.P
    - kernel.P
    - Motor.P
    - robolayer.P
    - serapp.P
    - Timer0.P
    - typeconv.P
    - Uart.P
    - xcs_cfg.P
  - build.err
  - build.lst
    - adc.lst
    - applic.lst
    - dbgext.lst
    - debugger.lst
    - delay.lst
    - eeprom.lst
    - fpga_cfg.lst
    - fpgassi.lst
    - kernel.lst
    - kernel.map
    - Motor.lst
    - robolayer.lst
    - serapp.lst
    - Timer0.lst
    - typeconv.lst
    - Uart.lst
    - xcs_cfg.lst
  - build.obj
    - adc.o
    - applic.o
    - dbgext.o
    - debugger.o
    - delay.o
    - eeprom.o
    - fpga_cfg.o
    - fpgassi.o
    - kernel.elf
    - kernel.o
    - kernel.obj
    - Motor.o
    - robolayer.o
    - serapp.o
    - Timer0.o
    - typeconv.o
    - Uart.o
    - xcs_cfg.o
  - build.rom
    - kernel.eep
    - kernel.rom
  - cfg
    - compile.in
    - compileflags.in
    - env.in
    - hw.in
    - srcobj.in
    - swdef.in
  - kernel_elf.aps
  - kernel_elf.aws
  - license.txt
  - makefile
  - src
    - applic
      - applic.c
      - applic.h
      - cfg
        
        fpga_cfg.c
        
        fpga_cfg.h
      - fpgassi.c
      - fpgassi.h
      - Kernel.c
      - robolayer.c
      - robolayer.h
      - serapp.c
      - serapp.h
    - debug
    - includes
    - periphext
      - asciitab.h
      - keymat44.c
      - keymat44.h
      - lcm_char.c
      - lcm_char.h
      - lpc.c
      - lpc.h
      - scard.c
      - scard.h
      - sst.c
      - sst.h
      - xcs_cfg.c
      - xcs_cfg.h
    - periphint
      - adc.c
      - adc.h
      - eeprom.c
      - eeprom.h
      - Motor.c
      - Motor.h
      - spi.c
      - spi.h
      - Timer0.c
      - Timer0.h
      - Timer1.c
      - Timer1.h
      - Uart.c
      - Uart.h
    - Utils
      - delay.c
      - delay.h
      - typeconv.c
      - typeconv.h

/***************************************************************************
 Project:		AVRILOS
 Title:			General purpose LPC bus implementation
 Author:		Ilias Alexopoulos
 Version:		2.00
 Last updated:	28-Oct-2010
 Target:		NA
 File:			lpc.c

* Support E-mail:
* avrilos@ilialex.gr
* 
* license: See license.txt on root directory (CDDL)
*

* DESCRIPTION
* LPC Bus implementation used for access LPC devices 
* 
***************************************************************************/

#include <avr/io.h>

#include "../includes/types.h"
#include "../includes/settings.h"


extern INT8U v_SysStat;

#define LPC_RD	0x04
#define LPC_WR	0x06
#define LPCLD(v,x) do {v &= 0xF0; v |= x & 0x0F;  } while(0)
#define LPCOUT (outp( inp(c_LPCDDR)  | BV(b_LAD0) | BV(b_LAD1) | BV(b_LAD2) | BV(b_LAD3), c_LPCDDR ) )
#define LPCIN (outp( inp(c_LPCDDR)  &  ~( BV(b_LAD0) | BV(b_LAD1) | BV(b_LAD2) | BV(b_LAD3)) , c_LPCDDR) )

#define	LPCClk	do{ sbi(c_LPCBPORT, b_LCLK); \
					cbi(c_LPCBPORT, b_LCLK); \
					}while(0)

//outp( (inp(c_LPCPORT) & ~( BV(b_LAD0) | BV(b_LAD1) | BV(b_LAD2) | BV(b_LAD3))) | (data & ( BV(b_LAD0) | BV(b_LAD1) | BV(b_LAD2) | BV(b_LAD3))), c_LPCPORT);
#define LPCDOUT(data) do { 					\
						outp( ( inp(c_LPCPORT) & 0xF0 ) | ( (data) & 0x0F ), c_LPCPORT);	\
						LPCClk;				\
					} while(0)
					
#define LPCDIN(data) do { 					\
						data = inp(c_LPCPIN) & ( BV(b_LAD0) | BV(b_LAD1) | BV(b_LAD2) | BV(b_LAD3) );	\
						LPCClk;				\
					} while(0)
					
#ifndef MOD_LPC_ON

void f_ConfigLPC(void) {}
void f_LPC_Write(INT32U addr, INT8U data) {}
INT8U f_LPC_Read(INT32U addr) { return 0; }

#else

void f_ConfigLPC(void) 
{
	LPCOUT;
	outp( inp(c_LPCBDDR) | BV(b_LCLK) | BV(b_LFRAME), c_LPCBDDR);
	outp( inp(c_LPCPORT) | BV(b_LAD0) | BV(b_LAD1) | BV(b_LAD2) | BV(b_LAD3) , c_LPCPORT);
	
}

void f_LPC_Write(INT32U addr, INT8U data) 
{
	INT8U lpc;
	INT8U i;
	
	lpc = inp(c_LPCPORT);
	
	/* LFRAME - START */
	LPCDOUT(0X00);
	LPCDOUT(LPC_WR);
	
	for(i=0; i<8; i++)
	{
		LPCDOUT(addr >> (28-4*i));
	}
	
	LPCDOUT(data);
	LPCDOUT(data >> 4);
	
	/* TAR */
	LPCDOUT(0x0F);
	/* TAR */
	LPCIN;
	LPCDIN(lpc);
	/* SYNC */
	LPCDIN(lpc);
	
	/* TAR */
	LPCOUT;	
	LPCDOUT(0x0F);
	/* TAR */
	LPCDOUT(0x0F);
	
	/* Dummy cycles */
	LPCDOUT(0x0F);
	LPCDOUT(0x0F);
	LPCDOUT(0x0F);
	LPCDOUT(0x0F);
	
}

INT8U f_LPC_Read(INT32U addr) 
{ 
	INT8U lpc;
	INT8U i;
	INT8U data;
	
	lpc = inp(c_LPCPORT);
	
	/* LFRAME - START */
	LPCDOUT(0x00);
	LPCDOUT(LPC_RD);
	
	for(i=0; i<8; i++)
	{
		LPCDOUT(addr >> (28-4*i) );
	}
	
	/* TAR */
	LPCDOUT(0x0F);
	/* TAR */
	LPCIN;
	LPCDIN(lpc);
	
	/* SYNC */
	LPCDIN(lpc);
	
	/* Data */
	LPCDIN(data);
	lpc = data;
	LPCDIN(data);
	data = (data << 4) | lpc;
	
	/* TAR */
	LPCOUT;	
	LPCDOUT(0x0F);
	/* TAR */
	LPCDOUT(0x0F);
	
	/* Dummy cycles */
	LPCDOUT(0x0F);
	LPCDOUT(0x0F);
	LPCDOUT(0x0F);
	LPCDOUT(0x0F);


	return data; 
}

#endif

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License

This article, along with any associated source code and files, is licensed under The Common Development and Distribution License (CDDL)

Written By

grilialex

Systems Engineer AI ZeroCaliber Ltd

Cyprus

More than 15 year of Embedded Systems development designing both hardware & software.
Experience with Product Development,lab prototypes and Automated Testers, Sensors, motors and System Engineering. Have used numerous micro-controllers/processors, DSP & FPGAs.

Please check AI ZeroCaliber if you need any help.
You may find also my personal site: Ilialex and my blog site: Ilialex Blog

Xilinx FPGA with AVRILOS

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