BPSK modulation. Why these particular values are used?

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VHDL

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Entity Declaration
entity bpsk_mod is
Port (
clk : in std_logic; -- Processing clock
valid_in : in std_logic; -- Input valid signal
data_in : in std_logic; -- Input data signal
reset : in std_logic; -- Asynchronous reset signal
valid_out : out std_logic; -- output valid signal
data_out_rl, data_out_ig : out std_logic_vector(15 downto 0) -- real and imaginary part of the output data
);
end bpsk_mod;
-- Architecture begins here
architecture Behavioral of bpsk_mod is
begin
process(clk, reset)
begin
if (reset = '1') then
valid_out <= '0';
data_out_rl <= (others => '0');
data_out_ig <= (others => '0');
elsif(clk'event and clk = '1')then
if(valid_in = '1') then
case data_in is
when '1' => data_out_rl <= x"c000";
data_out_ig <= x"0000"; -- Based on the input generating the
valid_out <= '1'; -- output signals
when '0' => data_out_rl <= x"4000";
data_out_ig <= x"0000";
valid_out <= '1';
when others => data_out_rl <= x"0000";
data_out_ig <= x"0000";
valid_out <= '1';
end case;
else
valid_out <= '0';
data_out_rl <= (others => '0');
data_out_ig <= (others => '0');
end if;
end if;
end process;
end Behavioral;

I have got this vhdl based BPSK code from a site. The code is understandable, but why c000 and 4000 being used for real parts and 0000 is used for imaginary variables...(I know that output of a modulation scheme is complex) But Why these particular values.....Do they represent two points in the constellation diagram of the BPSK modulation scheme?

Again BPSK is represented by changing phase of the carrier signal according to the change in bits of the input signal. That carrier signal cant be seen here.

What I have tried:

We have simulated the code and havent got any carrier signal whose phase is changing according to the input signal. It simply shows numbers...What is that?