So just to give an update I have managed to resolve this actually I have kind of forgot the matrix transpose.... :embarrassed:
Here is my solution:
making package using arrays as followed:
package newtype is
type row_1 is array(0 to 3) of integer;
type matrix_inter is array(0 to 3, 0 to 3) of integer;
end newtype;
then the design part:
entity test is
port(input: in matrix_inter;
clk: in std_logic);
end test;
architecture arch of test is
signal matrix : matrix_intert;
signal temp_row : row_1;
signal count : unsigned(1 downto 0) := "0";
function extract_row( m : matrix_inter; row : integer) return row_1 is
variable ret : row_1;
begin
for i in row_1'range loop
ret(i) := m(row, i);
end loop;
return ret;
end function;
begin
process(clk)
begin
if rising_edge(clk) then
temp_row <= extract_row( matrix, to_integer(count) );
count <= count + 1;
end if;
end process;
end arch;
and finally tb part:
entity test is
port(input: in matrix_inter;
clk: in std_logic);
end test;
architecture arch of test is
signal matrix : matrix_inter;
signal temp_row : row_1;
signal count : unsigned(1 downto 0) := "0";
function extract_row( m : matrix_inter; row : integer) return row_1 is
variable ret : row_1;
begin
for i in row_1'range loop
ret(i) := m(row, i);
end loop;
return ret;
end function;
begin
process(clk)
begin
if rising_edge(clk) then
temp_row <= extract_row( matrix, to_integer(count) );
count <= count + 1;
end if;
end process;
end arch;
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