(i)(CEngine): Creating source level (V&G)....
(i)(CircuitElement CE_NONAME.0): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.0): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Renaming...
(i)(CircuitElement Source(V&G).0): New name is OK.
(i)(Gate):(Type[Voltage],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[Ground],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(c)(CEngine): CE Empty:Source(V&G) is added into circuit.
(c)(CEngine): compilation started (D:\_Courses\CMPE40~1\CEngine.net\Release\DENEME~1.CES)....
Initializing BreadBoard Node Table(r50,c3)...
BreadBoard Node Table is ready.
Initializing BreadBoard Node Map Table(h7)...
BreadBoard Node Map Table is ready.
(i)(CircuitElement CE_NONAME.1): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.1): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Renaming...
(i)(CircuitElement GateTest.1): New name is OK.
(c)(CEngine): CE CHIP:GateTest is now setting up by in-script information ....
(i)(CircuitElement GateTest.1): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[11])::SetProps.() : properties OK.
(i)(CircuitElement GateTest.1): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[10])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[NAND],NofInputs[2],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[2],OutAsLeg[5])::SetProps.() : properties OK.
(i)(Gate):(Type[NOR],NofInputs[2],OutAsLeg[6])::SetProps.() : properties OK.
(i)(Gate):(Type[XOR],NofInputs[2],OutAsLeg[7])::SetProps.() : properties OK.
(i)(Gate):(Type[XNOR],NofInputs[2],OutAsLeg[8])::SetProps.() : properties OK.
(c)(CEngine): Gate List is OK for GateTest.1..
(c)(CEngine): Gate connection process is starting for GateTest.1....
(c)(CEngine): Gate connection process is completed..
(c)(CEngine): CE CHIP:GateTest is added into circuit.
(i)(CEngine): compilation completed....
LISTING CURRENT CIRCUIT ELEMENTS:
BREADBOARD : 50 rows, 3 cols and 7 holes in a node.
Gate List CE Source(V&G).id_0 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_0 (00000000), G = leg_0 (00000000)
Voltage(003C2580)(leg_0).1 >> 0 ()
Ground(003C25B8)(leg_0).2 >> 0 ()
Gate List CE GateTest.id_1 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_11 (00000000), G = leg_12 (00000000)
Input(003C8A80)(leg_1).1 >> 1 ( 00000000 )
Input(003C8AB8)(leg_2).2 >> 1 ( 00000000 )
NOT(003C8AF0)(leg_10).3 >> 1 ( 003C8AB8 )
AND(003C8B28)(leg_3).4 >> 2 ( 003C8A80 003C8AB8 )
NAND(003C8B60)(leg_4).5 >> 2 ( 003C8A80 003C8AB8 )
OR(003C8B98)(leg_5).6 >> 2 ( 003C8A80 003C8AB8 )
NOR(003C8BD0)(leg_6).7 >> 2 ( 003C8A80 003C8AB8 )
XOR(003C8C08)(leg_7).8 >> 2 ( 003C8A80 003C8AB8 )
XNOR(003C8C40)(leg_8).9 >> 2 ( 003C8A80 003C8AB8 )
END OF CIRCUIT LIST
Deallocating BreadBoard Node Table...
Deallocating BreadBoard Node Map Table...
Deallocation of BreadBoard is completed.