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signed char ch;
short int a = 220;

I have return the above c program to assign a short int to a signed char as below.

ch = a; //assigning short int to signed char variable ch;

Below is the assembly code generated for the assignment statement.


MOV R2, R6, LSL 24 R6 contain a which is 220
MOV R0, R0
MOV R2, R2, ASR 24
STRB R2,[SP,3]

I have understood that R6 is Left shifted by 24 bit and Aritmetic right shift by 24 bit to get the signed byte value which is stored in the stack.
But i don't understood why a NOP kind of instruction is generated in between the two MOV operaation.
Generally NOP instruction is used to introduce some delay in programming to wait until some operation has completed.
But here why MOV R0,R0 is generated what is the significance?

Please some one clarify.
Posted

Flags.
It clears the Carry flag, so that it isn't propagated by the right shift into the resulting value.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/BABJAJIB.html[^]
 
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chandrAN2& 25-Nov-15 12:51pm    
Understood , thanks. If carry flag is not cleared, did ASR instruction use the carry bit vale while right shifting?
OriginalGriff 25-Nov-15 14:03pm    
Yes - just look at the ARM documentation.
Generally "nop" instructions are introduced into debug versions of the compiled executable for :
1) aligning to byte boundaries for internal cache structures for better loading.
2) a place holder for debugging breakpoints for debuggers.
3) handling known timing issues on processors.
 
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chandrAN2& 25-Nov-15 6:44am    
Thanks for the info, but in the above case what is the reason for the NOP in between. There is no alignment problem here, all are 4byte ARM instructions.
And Debugging related options are not enabled here. Final is the timing issues which i don't understand,you mean due to pipelining, result may not be available for the next operation?Is that what you say. For that nop is not needed, this only results in pipeline stall for few cycles or instruction scheduling should change, compiler optimization will come into picture for instrcution scheduling. But i don't exactly get the reason for the above code generation.
If a NOP is not implemented on the target processor, it may do this. See this link here[^].
 
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