(i)(CEngine): Creating source level (V&G)....
(i)(CircuitElement CE_NONAME.0): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.0): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Renaming...
(i)(CircuitElement Source(V&G).0): New name is OK.
(i)(Gate):(Type[Voltage],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[Ground],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(c)(CEngine): CE Empty:Source(V&G) is added into circuit.
(c)(CEngine): compilation started (D:\_Courses\_PASTU~1\DO6114~1\CMPE40~1\CEngine.net\Release\PAGE58~1.CES)....
Initializing BreadBoard Node Table(r20,c3)...
BreadBoard Node Table is ready.
Initializing BreadBoard Node Map Table(h5)...
BreadBoard Node Map Table is ready.
(i)(CircuitElement CE_NONAME.1): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.1): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Renaming...
(i)(CircuitElement EX.PAGE58.1): New name is OK.
(c)(CEngine): CE CHIP:EX.PAGE58 is now setting up by in-script information ....
(i)(CircuitElement EX.PAGE58.1): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[6])::SetProps.() : properties OK.
(i)(CircuitElement EX.PAGE58.1): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[2],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[2],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[2],OutAsLeg[5])::SetProps.() : properties OK.
(c)(CEngine): Gate List is OK for EX.PAGE58.1..
(c)(CEngine): Gate connection process is starting for EX.PAGE58.1....
(c)(CEngine): Gate connection process is completed..
(c)(CEngine): CE CHIP:EX.PAGE58 is added into circuit.
(i)(CEngine): compilation completed....
LISTING CURRENT CIRCUIT ELEMENTS:
BREADBOARD : 20 rows, 3 cols and 5 holes in a node.
Gate List CE Source(V&G).id_0 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_0 (00000000), G = leg_0 (00000000)
Voltage(003C2580)(leg_0).1 >> 0 ()
Ground(003C25B8)(leg_0).2 >> 0 ()
Gate List CE EX.PAGE58.id_1 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_6 (00000000), G = leg_3 (00000000)
Input(003C7608)(leg_1).1 >> 1 ( 00000000 )
Input(003C7640)(leg_2).2 >> 1 ( 00000000 )
AND(003C7678)(leg_0).3 >> 2 ( 003C7758 003C7608 )
OR(003C76B0)(leg_0).4 >> 2 ( 003C7640 003C7790 )
AND(003C76E8)(leg_0).5 >> 2 ( 003C7640 003C7758 )
OR(003C7720)(leg_0).6 >> 2 ( 003C7608 003C7790 )
AND(003C7758)(leg_4).7 >> 2 ( 003C7678 003C76B0 )
OR(003C7790)(leg_5).8 >> 2 ( 003C76E8 003C7720 )
END OF CIRCUIT LIST
Deallocating BreadBoard Node Table...
Deallocating BreadBoard Node Map Table...
Deallocation of BreadBoard is completed.