(i)(CEngine): Creating source level (V&G)....
(i)(CircuitElement CE_NONAME.0): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.0): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.0): Renaming...
(i)(CircuitElement Source(V&G).0): New name is OK.
(i)(Gate):(Type[Voltage],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[Ground],NofInputs[0],OutAsLeg[0])::SetProps.() : properties OK.
(c)(CEngine): CE Empty:Source(V&G) is added into circuit.
(c)(CEngine): File is reading now (D:\_Courses\CMPE40~1\CEngine.net\Release\DUAL4I~1\DUAL4I~1.cec)....
(c)(CEngine): File ID is OK, the Circuit is Loading....
(c)(CEngine): Setting up the BreadBoard information....
Initializing BreadBoard Node Table(r30,c4)...
BreadBoard Node Table is ready.
Initializing BreadBoard Node Map Table(h6)...
BreadBoard Node Map Table is ready.
(c)(CEngine): BreadBoard is ready..
(i)(CircuitElement CE_NONAME.1): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.1): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.1): Renaming...
(i)(CircuitElement Dual4InputMux.1): New name is OK.
(i)(CircuitElement Dual4InputMux.1): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[16])::SetProps.() : properties OK.
(i)(CircuitElement Dual4InputMux.1): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[8])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[3])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[4])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[5])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[6])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[10])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[11])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[13])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[14])::SetProps.() : properties OK.
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[15])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[NOT],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[AND],NofInputs[4],OutAsLeg[0])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[4],OutAsLeg[7])::SetProps.() : properties OK.
(i)(Gate):(Type[OR],NofInputs[4],OutAsLeg[9])::SetProps.() : properties OK.
(c)(CEngine): CE CHIP:Dual4InputMux is added into circuit.
(i)(CircuitElement CE_NONAME.2): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.2): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.2): Renaming...
(i)(CircuitElement .2): New name is OK.
(i)(CircuitElement .2): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[15])::SetProps.() : properties OK.
(i)(CircuitElement .2): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .2): Renaming...
(i)(CircuitElement CABLE.2): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.3): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.3): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.3): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.3): Renaming...
(i)(CircuitElement .3): New name is OK.
(i)(CircuitElement .3): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[15])::SetProps.() : properties OK.
(i)(CircuitElement .3): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .3): Renaming...
(i)(CircuitElement CABLE.3): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.4): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.4): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.4): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.4): Renaming...
(i)(CircuitElement .4): New name is OK.
(i)(CircuitElement .4): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(CircuitElement .4): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .4): Renaming...
(i)(CircuitElement CABLE.4): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.5): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.5): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.5): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.5): Renaming...
(i)(CircuitElement .5): New name is OK.
(i)(CircuitElement .5): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(CircuitElement .5): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .5): Renaming...
(i)(CircuitElement CABLE.5): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.6): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.6): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.6): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.6): Renaming...
(i)(CircuitElement .6): New name is OK.
(i)(CircuitElement .6): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(CircuitElement .6): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .6): Renaming...
(i)(CircuitElement CABLE.6): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.7): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.7): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.7): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.7): Renaming...
(i)(CircuitElement LED.7): New name is OK.
(i)(CircuitElement LED.7): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[1])::SetProps.() : properties OK.
(i)(CircuitElement LED.7): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[2])::SetProps.() : properties OK.
(c)(CEngine): CE LED:LED is added into circuit.
(i)(CircuitElement CE_NONAME.8): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.8): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.8): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.8): Renaming...
(i)(CircuitElement .8): New name is OK.
(i)(CircuitElement .8): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[11])::SetProps.() : properties OK.
(i)(CircuitElement .8): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .8): Renaming...
(i)(CircuitElement CABLE.8): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.9): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.9): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.9): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.9): Renaming...
(i)(CircuitElement .9): New name is OK.
(i)(CircuitElement .9): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(CircuitElement .9): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .9): Renaming...
(i)(CircuitElement CABLE.9): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.10): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.10): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.10): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.10): Renaming...
(i)(CircuitElement .10): New name is OK.
(i)(CircuitElement .10): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[12])::SetProps.() : properties OK.
(i)(CircuitElement .10): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .10): Renaming...
(i)(CircuitElement CABLE.10): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.11): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.11): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.11): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.11): Renaming...
(i)(CircuitElement .11): New name is OK.
(i)(CircuitElement .11): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[15])::SetProps.() : properties OK.
(i)(CircuitElement .11): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .11): Renaming...
(i)(CircuitElement CABLE.11): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.12): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.12): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.12): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.12): Renaming...
(i)(CircuitElement
.12): New name is OK.
(i)(CircuitElement
.12): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[15])::SetProps.() : properties OK.
(i)(CircuitElement
.12): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement
.12): Renaming...
(i)(CircuitElement CABLE.12): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.13): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.13): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.13): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.13): Renaming...
(i)(CircuitElement .13): New name is OK.
(i)(CircuitElement .13): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[15])::SetProps.() : properties OK.
(i)(CircuitElement .13): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .13): Renaming...
(i)(CircuitElement CABLE.13): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.14): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.14): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.14): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.14): Renaming...
(i)(CircuitElement .14): New name is OK.
(i)(CircuitElement .14): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[15])::SetProps.() : properties OK.
(i)(CircuitElement .14): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .14): Renaming...
(i)(CircuitElement CABLE.14): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(i)(CircuitElement CE_NONAME.15): New circuit element requested. initializing...
(i)(CircuitElement CE_NONAME.15): Voltage leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.15): Ground leg is creating...
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement CE_NONAME.15): Renaming...
(i)(CircuitElement .15): New name is OK.
(i)(CircuitElement .15): Setting Voltage Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[15])::SetProps.() : properties OK.
(i)(CircuitElement .15): Setting Ground Leg Association
(i)(Gate):(Type[Input],NofInputs[1],OutAsLeg[0])::SetProps.() : properties OK.
(i)(CircuitElement .15): Renaming...
(i)(CircuitElement CABLE.15): New name is OK.
(c)(CEngine): CE CABLE:CABLE is added into circuit.
(c)(CEngine): In-CircuitElement connections completed, printing retrieved circuit (D:\_Courses\CMPE40~1\CEngine.net\Release\DUAL4I~1\DUAL4I~1.cec).
LISTING CURRENT CIRCUIT ELEMENTS:
BREADBOARD : 30 rows, 4 cols and 6 holes in a node.
Gate List CE Source(V&G).id_0 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_0 (00000000), G = leg_0 (00000000)
Voltage(003C2580)(leg_0).1 >> 0 ()
Ground(003C25B8)(leg_0).2 >> 0 ()
Gate List CE Dual4InputMux.id_1 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_16 (00000000), G = leg_8 (00000000)
Input(003C7140)(leg_1).1 >> 1 ( 00000000 )
Input(003C7178)(leg_2).2 >> 1 ( 00000000 )
Input(003C71B0)(leg_3).3 >> 1 ( 00000000 )
Input(003C71E8)(leg_4).4 >> 1 ( 00000000 )
Input(003C7220)(leg_5).5 >> 1 ( 00000000 )
Input(003C7258)(leg_6).6 >> 1 ( 00000000 )
Input(003C7290)(leg_10).7 >> 1 ( 00000000 )
Input(003C72C8)(leg_11).8 >> 1 ( 00000000 )
Input(003C7300)(leg_12).9 >> 1 ( 00000000 )
Input(003C7338)(leg_13).10 >> 1 ( 00000000 )
Input(003C7370)(leg_14).11 >> 1 ( 00000000 )
Input(003C73A8)(leg_15).12 >> 1 ( 00000000 )
NOT(003C73E0)(leg_0).13 >> 1 ( 003C7140 )
NOT(003C7418)(leg_0).14 >> 1 ( 003C7178 )
NOT(003C7450)(leg_0).15 >> 1 ( 003C7370 )
NOT(003C7488)(leg_0).16 >> 1 ( 003C73A8 )
NOT(003C74C0)(leg_0).17 >> 1 ( 003C7178 )
NOT(003C74F8)(leg_0).18 >> 1 ( 003C71B0 )
AND(003C7530)(leg_0).19 >> 4 ( 003C7140 003C7178 003C71B0 003C7258 )
AND(003C7570)(leg_0).20 >> 4 ( 003C7140 003C7178 003C7258 003C7220 )
AND(003C75B0)(leg_0).21 >> 4 ( 003C7140 003C7220 003C71B0 003C71E8 )
AND(003C75F0)(leg_0).22 >> 4 ( 003C7140 003C7220 003C7258 003C71B0 )
AND(003C7630)(leg_0).23 >> 4 ( 003C7290 003C7178 003C71B0 003C71E8 )
AND(003C7670)(leg_0).24 >> 4 ( 003C72C8 003C7178 003C7258 003C71E8 )
AND(003C76B0)(leg_0).25 >> 4 ( 003C7300 003C7220 003C71B0 003C71E8 )
AND(003C76F0)(leg_0).26 >> 4 ( 003C7338 003C7220 003C7258 003C71E8 )
OR(003C7730)(leg_7).27 >> 4 ( 003C7140 003C7178 003C71B0 003C71E8 )
OR(003C7770)(leg_9).28 >> 4 ( 003C7220 003C7258 003C7290 003C72C8 )
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : LED
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
END OF CIRCUIT LIST
(c)(CEngine): (Re)plugging process is initiated (D:\_Courses\CMPE40~1\CEngine.net\Release\DUAL4I~1\DUAL4I~1.cec).
(c)(CEngine): Plugging Dual4InputMux.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging LED.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): Plugging CABLE.
(c)(CEngine): (Re)plugging process is completed.
(c)(CEngine): Circuit is printing after (replugging process).
LISTING CURRENT CIRCUIT ELEMENTS:
BREADBOARD : 30 rows, 4 cols and 6 holes in a node.
Gate List CE Source(V&G).id_0 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_0 (00000000), G = leg_0 (00000000)
Voltage(003C2580)(leg_0).1 >> 0 ()
Ground(003C25B8)(leg_0).2 >> 0 ()
Gate List CE Dual4InputMux.id_1 [gtType(Addr).no >> nof_inputs (input addr. list)]
V = leg_16 (003C2580), G = leg_8 (003C25B8)
Input(003C7140)(leg_1).1 >> 1 ( 00000000 )
Input(003C7178)(leg_2).2 >> 1 ( 00000000 )
Input(003C71B0)(leg_3).3 >> 1 ( 00000000 )
Input(003C71E8)(leg_4).4 >> 1 ( 00000000 )
Input(003C7220)(leg_5).5 >> 1 ( 00000000 )
Input(003C7258)(leg_6).6 >> 1 ( 00000000 )
Input(003C7290)(leg_10).7 >> 1 ( 00000000 )
Input(003C72C8)(leg_11).8 >> 1 ( 00000000 )
Input(003C7300)(leg_12).9 >> 1 ( 00000000 )
Input(003C7338)(leg_13).10 >> 1 ( 00000000 )
Input(003C7370)(leg_14).11 >> 1 ( 00000000 )
Input(003C73A8)(leg_15).12 >> 1 ( 003C25B8 )
NOT(003C73E0)(leg_0).13 >> 1 ( 003C7140 )
NOT(003C7418)(leg_0).14 >> 1 ( 003C7178 )
NOT(003C7450)(leg_0).15 >> 1 ( 003C7370 )
NOT(003C7488)(leg_0).16 >> 1 ( 003C73A8 )
NOT(003C74C0)(leg_0).17 >> 1 ( 003C7178 )
NOT(003C74F8)(leg_0).18 >> 1 ( 003C71B0 )
AND(003C7530)(leg_0).19 >> 4 ( 003C7140 003C7178 003C71B0 003C7258 )
AND(003C7570)(leg_0).20 >> 4 ( 003C7140 003C7178 003C7258 003C7220 )
AND(003C75B0)(leg_0).21 >> 4 ( 003C7140 003C7220 003C71B0 003C71E8 )
AND(003C75F0)(leg_0).22 >> 4 ( 003C7140 003C7220 003C7258 003C71B0 )
AND(003C7630)(leg_0).23 >> 4 ( 003C7290 003C7178 003C71B0 003C71E8 )
AND(003C7670)(leg_0).24 >> 4 ( 003C72C8 003C7178 003C7258 003C71E8 )
AND(003C76B0)(leg_0).25 >> 4 ( 003C7300 003C7220 003C71B0 003C71E8 )
AND(003C76F0)(leg_0).26 >> 4 ( 003C7338 003C7220 003C7258 003C71E8 )
OR(003C7730)(leg_7).27 >> 4 ( 003C7140 003C7178 003C71B0 003C71E8 )
OR(003C7770)(leg_9).28 >> 4 ( 003C7220 003C7258 003C7290 003C72C8 )
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : LED
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
Empty CE : CABLE
END OF CIRCUIT LIST
Deallocating BreadBoard Node Table...
Deallocating BreadBoard Node Map Table...
Deallocation of BreadBoard is completed.